10

MITSUBISHI ELECTRIC

Jul. '01 Preliminary

MITSUBISHI LSIs

DDR SDRAM (Rev.1.0)

M2S56D20/ 30/ 40AKT

256 M Double Data Rate Synchronous DRAM

FUNCTION TRUTH TABLE (continued)

ABBREVIATIONS:

H=High Level, L=Low Level, X=Don't Care

BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation

NOTES:

1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.

2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of

that bank.

3. Must satisfy bus contention, bus turn around, write recovery requirements.

4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.

5. ILLEGAL if any bank is not idle.

6. Refer to Read with Auto -Precharge in page 24.

7. Refer to Write with Auto-Precharge in page 26.

ILLEGAL = Device operation and/or data-integrity are not guaranteed.

Current State

/CS /RAS /CAS /WE Address

Command

Action

Notes

REFRESHING

H

X

X

X

X

DESEL

NOP (Idle after tRC)

L

H

H

H

X

NOP

NOP (Idle after tRC)

L

H

H

L

BA

TERM

ILLEGAL

L

H

L

X

BA, CA, A10

READ / WRITE

ILLEGAL

L

L

H

H

BA, RA

ACT

ILLEGAL

L

L

H

L

BA, A10

PRE / PREA

ILLEGAL

L

L

L

H

X

REFA

ILLEGAL

L

L

L

L

Op-Code, Mode-

Add

MRS

ILLEGAL

H

X

X

X

X

DESEL

NOP (Row Active after tRSC)

L

H

H

H

X

NOP

NOP (Row Active after tRSC)

L

H

H

L

BA

TERM

ILLEGAL

L

H

L

X

BA, CA, A10

READ / WRITE

ILLEGAL

L

L

H

H

BA, RA

ACT

ILLEGAL

L

L

H

L

BA, A10

PRE / PREA

ILLEGAL

L

L

L

H

X

REFA

ILLEGAL

L

L

L

L

Op-Code, Mode-

Add

MRS

ILLEGAL

MODE

REGISTER

SETTING