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LTC4231 Datasheet(PDF) 9 Page - Linear Technology

Part # LTC4231
Description  Micropower Hot Swap Controller
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC4231 Datasheet(HTML) 9 Page - Linear Technology

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LTC4231
9
4231f
For more information www.linear.com/LTC4231
ThemicropowercapabilityoftheLTC4231makesitidealfor
Hot Swap applications in battery powered systems where
current load is light or intermittent and power draw is a
concern. It can implement battery short circuit protection,
reverse battery protection, battery voltage monitoring,
power path control, hot-plug and inrush current control
in off-grid, autonomous systems.
Turn-On Sequence
When IN is less than the UVLO level of 2.3V or SHDN is
low, GATE is pulled to GND and STATUS pulls low. When
IN ≥ 2.3V and SHDN goes high, an internal clock starts
timing a 40ms debounce cycle. The clock also times a
200µs strobe of the resistive divider at IN every 10ms
to make sure IN is not in OV/UV. Average ICC during this
debounce mode is 4µA.
AnyOV/UVdetectedwillstopandresetthedebouncetiming
cycle. During this voltage fault mode, average ICC is 4µA.
The debounce cycle only restarts when a subsequent IN
strobe indicates that the input power is within the accept-
able range, IN ≥ 2.3V and SHDN is high.
Whenthedebouncecycleof40mssuccessfullycompletes,
the LTC4231 turns on its charge pump, analog current
limit amplifier and TIMER control circuit blocks as it goes
applicaTions inForMaTion
into start-up mode (ICC = 300µA). The external MOSFET
is turned on by charging up the GATE with a 10μA charge
pump generated current source.
At start-up, the MOSFET current is typically dominated by
the current charging the load capacitor CL. If ∆VSENSE >
80mV, the analog current limit amplifier controls the gate
of the MOSFET in a closed loop. This keeps the start-up
inrush current at 80mV/RSENSE. When ∆VSENSE > 50mV,
the TIMER capacitor charges up with an internal 50µA
pull-up current.
Figure 2. Inrush Control by Analog Current Limit
SENSE
GATE
IN
UVL
UVH
OV
GNDSW
SOURCE
STATUS
SHDN
TIMER
LTC4231
M1
Si7120ADN
RSENSE
22.5m
GND
RSTAT
20k
R5
2M
C1
1nF
R5
10Ω
CG
20nF
VOUT
24V
2A
GND
R1
1020k
Z1
SMAJ24A
CIN
100µF
R2
1.65k
24V
BATTERY
CELL(S)
UV RISING = 23V
UV FALLING = 22V
OV RISING = 26V
R3
4.22k
R4
32.4k
CT
39nF
ILOAD
4231 F01
RG
1k
R7
10M
+
+
CL
1000µF
Figure 1. Channel Controller with Connector Enable
GATE
20V/DIV
OUT
20V/DIV
TIMER
0.5V/DIV
ILOAD
2A/DIV
1ms/DIV
START-UP
NORMAL ON
DEBOUNCE
4231 F02


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