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D784927YGF101 Datasheet(PDF) 3 Page - NEC |
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D784927YGF101 Datasheet(HTML) 3 Page - NEC |
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3 / 96 page  3 µPD784927, 784928, 784927Y, 784928Y Data Sheet U12255EJ2V0DS00 µPD784927, 784927Y µPD784928, 784928Y 96K bytes 128K bytes 2048 bytes 3584 bytes 16 MHz (internal clock: 8 MHz) Low frequency oscillation mode : 8 MHz (internal clock: 8 MHz) Low power consumption mode : 32.768 kHz (subsystem clock) 250 ns (with 8 MHz internal clock) 74 input : 20 I/O : 54 (including 8 ports for LED direct drive) 11 (including one each for pseudo VSYNC, head amplifier switch, and chrominance rotation) Timer/counter Compare register Capture register Remark TM0 (16 bits) 3 — TM1 (16 bits) 3 1 FRC (22 bits) — 6 TM3 (16 bits) 2 1 UDC (5 bits) 1 — EC (8 bits) 4 — For HSW signal generation EDV (8 bits) 1 — For CFG signal division Input signal Number of bits Measurable cycle Operating edge CFG 22 125 ns to 524 ms ↑↓ DFG 22 125 ns to 524 ms ↑ HSW 16 1 µs to 65.5 ms ↑↓ VSYNC 22 125 ns to 524 ms ↑ CTL 16 1 µs to 65.5 ms ↑↓ TREEL 22 125 ns to 524 ms ↑↓ SREEL 22 125 ns to 524 ms ↑↓ • VSYNC separation circuit, HSYNC separation circuit • VISS detection, wide aspect detection circuits • Field identification circuit • Head amplifier switch/chrominance rotation output circuit Timer Compare register Capture register TM2 (16 bits) 1 — TM4 (16 bits) 1 (capture/compare) 1 TM5 (16 bits) 1 — • 16-bit resolution : 3 channels (carrier frequency: 62.5 kHz) • 8-bit resolution : 3 channels (carrier frequency: 62.5 kHz) 3-wire serial I/O: 2 channels (BUSY/STRB control: 1 channel) • I2C bus interface: 1 channel ( µPD784928Y subseries only) 8-bit resolution × 12 channels, conversion time: 10 µs FUNCTION LIST (1/2) Part Number Item Internal ROM capacity Internal RAM capacity Operating clock Minimum instruction execu- tion time I/O port Real-time output port Timer/counter Capture register VCR special circuit General-purpose timer PWM output Serial interface A/D converter Super timer unit |
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