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LXC8192 Datasheet(PDF) 6 Page - Level One |
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LXC8192 Datasheet(HTML) 6 Page - Level One |
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6 / 18 page  /;7êíè$ ,QWHJUDWHG 7ìî(ì 6KRUWð+DXO 7UDQVFHLYHU ZLWK 7UDQVPLW -$ ëðéé L1 7UDQVPLWWHU Data received for transmission onto the line is clocked seri- ally into the device at TPOS and TNEG. Input synchroni- zation is supplied by the transmit clock (TCLK). The transmitted pulse shape is determined by Equalizer Control signals EC1 through EC3 as shown in Table 4. Refer to Test Specifications for master and transmit clock timing characteristics. Shaped pulses are applied to the AMI line driver for transmission onto the line at TTIP and TRING. Equalizer Control signals may be hardwired in the Hard- ware Mode, or input as part of the serial data stream (SDI) in the Host Mode Pulses can be shaped for either 1.544 or 2.048 Mbps appli- cations. 1.544 Mbps pulses for DSX-1 applications can be programmed to match line lengths from 0 to 655 feet of ABAM cable. The LXT305A also matches FCC and ECSA specifications for CSU applications. 2.048 Mbps pulses can drive coaxial or shielded twisted-pair lines. -LWWHU $WWHQXDWLRQ Jitter attenuation of the LXT305A transmit outputs is pro- vided by a Jitter Attenuation Loop (JAL) and an Elastic Store (ES). An external crystal oscillating at 4 times the bit rate provides clock stabilization. Refer to Application Information for crystal specifications. The ES is a 32 x 2- bit register. Transmit data is clocked into the ES with the transmit clock (TCLK) signal, and clocked out of the ES with the dejittered clock from the JAL. When the bit count in the ES is within two bits of overflowing or underflowing, the ES adjusts the output clock by 1/8 of a bit period. The ES produces an average delay of 16 bits in the receive path. 'ULYHU 3HUIRUPDQFH 0RQLWRU 7KH WUDQVFHLYHU LQFRUSRUDWHV D 'ULYHU 3HUIRUPDQFH 0RQLð WRU õ'30ô LQ SDUDOOHO ZLWK 77,3 DQG 75,1* DW WKH RXWSXW WUDQVIRUPHUï 7KH '30 RXWSXW JRHV +LJK XSRQ GHWHFWLRQ RI çê FRQVHFXWLYH ]HURVï ,W LV UHVHW ZKHQ D RQH LV GHWHFWHG RQ WKH WUDQVPLW OLQHñ RU ZKHQ D UHVHW FRPPDQG LV UHFHLYHGï /LQH &RGH The LXT305A transmits data as a 50% AMI line code as shown in Figure 2. The output driver maintains a constant low output impedance regardless of whether it is driving marks or spaces. This well controlled output impedance provides excellent return loss (> 18 dB) when used with external 9.1 ″ precision (± 1 % accuracy) in series with a transmit transformer with a turns ratio of 1:2.3 (± 2% accu- racy). Series resistors also provide increased surge protec- tion and reduced short circuit current flow. )LJXUH ëã èíø $0, &RGLQJ 2SHUDWLQJ 0RGHV The LXT305A can be controlled through hard-wired pins (Hardware Mode) or by a microprocessor through a serial interface (Host Mode). The mode of operation is set by the MODE pin logic level. The LXT305A can also be com- manded to operate in one of several diagnostic modes. 7DEOH ëã /;7êíè$ 6HULDO 'DWD 2XWSXW %LWV õ6HH )LJXUH éô %LW 'è %LW 'ç %LW 'æ 6WDWXV í í í 5HVHW KDV RFFXUUHGñ RU QR SURJUDP LQSXWï í í ì 7$26 LV DFWLYHï í ì í /RFDO /RRSEDFN LV DFWLYHï í ì ì 7$26 DQG /RFDO /RRSEDFN DUH DFWLYHï ì í í 5HPRWH /RRSEDFN LV DFWLYHï ì í ì '30 KDV FKDQJHG VWDWH VLQFH ODVW &OHDU '30 RFFXUUHGï ì ì í /26 KDV FKDQJHG VWDWH VLQFH ODVW &OHDU /26 RFFXUUHGï ì ì ì /26 DQG '30 KDYH ERWK FKDQJHG VWDWH VLQFH ODVW &OHDU '30 DQG &OHDU /26 RFFXUUHGï 77,3 %LW &HOO ì ì í 75,1* |
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