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RT9728 Datasheet(PDF) 9 Page - Richtek Technology Corporation

Part # RT9728
Description  The RT9728 is a cost effective
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Manufacturer  RICHTEK [Richtek Technology Corporation]
Direct Link  http://www.richtek.com
Logo RICHTEK - Richtek Technology Corporation

RT9728 Datasheet(HTML) 9 Page - Richtek Technology Corporation

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RT9728
9
DS9728-05
October 2014
www.richtek.com
©
Copyright
2014 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
capacitor itself should have a low dissipation factor to allow
decoupling at higher frequencies.
Chip Enable Input
The RT9728 will be disabled when the EN pin is in a logic
low condition. During this condition, the internal circuitry
and MOSFET are turned off, reducing the supply current
to 1
μA typical. The maximum guaranteed voltage for a
logic-low at the EN pin is 0.66V. A minimum guaranteed
voltage of 1.1V at the EN pin will turn off the RT9728.
Floating the input may cause unpredictable operation. EN
should not be allowed to go negative with respect to GND.
Under Voltage Lockout
Under Voltage Lockout (UVLO) prevents the MOSFET
switch from turning on until input voltage exceeds
approximately 2.3V. If input voltage drops below
approximately 2.1V, UVLO turns off the MOSFET switch
and FAULT will be asserted accordingly. The under voltage
lockout detection functions only when the switch is
enabled.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX)
− TA) / θJA
where TJ(MAX) is the maximum junction temperature, TAis
the ambient temperature, and
θJAis the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125
°C. The junction to
ambient thermal resistance,
θJA, is layout dependent. For
WDFN-6L 2x2 packages, the thermal resistance,
θJA, is
165
°C/W on a standard JEDEC 51-3 single layer thermal
test board. The maximum power dissipation at TA = 25
°C
can be calculated by the following formula :
PD(MAX) = (125
°C − 25°C) / (165°C/W) = 0.606W for
WDFN-6L 2x2 package
Fault Flag
The RT9728 provides a FAULT signal pin which is an N-
Channel open drain MOSFET output. This open drain
output goes low when current exceeds current limit
threshold. The FAULT output is capable of sinking a 1mA
load to typically 180mV above ground. The FAULT pin
requires a pull-up resistor ; this resistor should be large
in value to reduce energy drain. A 100k
Ω pull-up resistor
works well for most applications. In case of an over current
condition, FAULT will be asserted only after the flag
response delay time, tD, has elapsed. This ensures that
FAULT is asserted upon valid over current conditions and
that erroneous error reporting is eliminated. For example,
false over current conditions may occur during hot-plug
events when extremely large capacitive loads are
connected, which induces a high transient inrush current
that exceeds the current limit threshold. The FAULT
response delay time, tD, is typically 7.5ms.
Supply Filter/Bypass Capacitor
A 10
μF low-ESR ceramic capacitor connected from VIN to
GND and located close to the device is strongly
recommended to prevent input voltage drooping during hot-
plug events. However, higher capacitor values may be used
to further reduce the voltage droop on the input. Without
this bypass capacitor, an output short may cause sufficient
ringing on the input (from source lead inductance) to
destroy the internal control circuitry. Note that the input
transient voltage must never exceed 6V as stated in the
Absolute Maximum Ratings.
Output Filter Capacitor
A low-ESR 150
μF aluminum electrolytic capacitor
connected between VOUT and GND is strongly
recommended to meet the USB standard maximum droop
requirement for the hub, VBUS. Standard bypass methods
should be used to minimize inductance and resistance
between the bypass capacitor and the downstream
connector to reduce EMI and decouple voltage droop
caused by hot-insertion transients in downstream cables.
Ferrite beads in series with VBUS, the ground line and the
0.1
μF bypass capacitors at the power connector pins are
recommended for EMI and ESD protection. The bypass


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