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SZA2044ZSR Datasheet(PDF) 7 Page - RF Micro Devices |
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SZA2044ZSR Datasheet(HTML) 7 Page - RF Micro Devices |
7 / 12 page 7 of 12 DS121211 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. SZA-2044(Z) Pin Names and Descriptions Pin Name Description 1, 2, 4, 5, 7, 9, 11, 13, 15, 17, 19 N/C These are unused pins and not wired inside the package. They may be grounded or connected to adjacent pins. 6VPC1 VPC1 is the bias control pin for the stage 1 active bias circuit. An external series resistor is required for proper setting of bias levels. Refer to the evaluation board schematic for resistor value. To prevent potential damage, do not apply voltage to this pin that is +1V greater than voltage applied to pin 20 (Vbias) unless Vpc supply current capability is less than 10mA. 8VPC2 VPC2 is the bias control pin for the stage 2 active bias circuit. An external series resistor is required for proper setting of bias levels. Refer to the evaluation board schematic for resistor value. To prevent potential damage, do not apply voltage to this pin that is +1V greater than voltage applied to pin 20 (Vbias) unless Vpc supply current capability is less than 10mA. 10 VDET Output power detector voltage. Load with >10K for best performance 3RF IN RF input pin. This is DC grounded internal to the IC. Do not apply voltage to this pin. 12,14 RF OUT RF output pin. This is also another connection to the 2nd stage collector. 16 VC2 2nd stage collector bias pin. Apply 3.0V to 5.0V to this pin. 18 VC1 1st stage collector bias pin. Apply 3.0V to 5.0V to this pin. 20 VBIAS Active bias network VCC. Apply 3.0V to 5.0V to this pin. EPAD GND Exposed area on the bottom side of the package needs to be soldered to the ground plane of the board for optimum ther- mal and RF performance. Several vias should be located under the EPAD as shown in the recommended land pattern. |
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