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P3C1021 Datasheet(PDF) 1 Page - Pyramid Semiconductor Corporation |
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P3C1021 Datasheet(HTML) 1 Page - Pyramid Semiconductor Corporation |
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1 / 10 page  1 Document # SRAM134 REV OR Revised April 2007 P3C1021 HIGH SPEED 64K x 16 (1 MEG) STATIC CMOS RAM High Speed (Equal Access and Cycle Times) — 10/12/15/20 ns (Commercial) — 12/15/20 ns (Industrial) Low Power — 325 mW (max.) Single 3.3V ± 0.3V Power Supply Easy Memory Expansion Using CE CE CE CE CE and OE OE OE OE OE Inputs FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION 1519B FEATURES DESCRIPTION The P3C1021 is a 65,536 words by 16 bits high-speed CMOS static RAM. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM oper- ates from a single 3.3V ± 0.3V tolerance power supply. Access times as fast as 10 nanoseconds permit greatly enhanced system operating speeds. CMOS is utilized to reduce power consumption to a low level. The P3C1021 is a member of a family of PACE RAM™ products offer- ing fast access times. The P3C1021 device provides asynchronous operation with matching access and cycle times. Memory loca- tions are specified on address pins A 0 to A15. Reading is accomplished by device selection (CE and output en- abling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE or OE is HIGH or WE is LOW. Package options for the P3C1021 include 44-pin SOJ and TSOP packages. Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Fast t OE Automatic Power Down when deselected Packages —44-Pin SOJ, TSOP II SOJ TSOPII |
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