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P4C1299-20PMB Datasheet(PDF) 4 Page - Pyramid Semiconductor Corporation |
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P4C1299-20PMB Datasheet(HTML) 4 Page - Pyramid Semiconductor Corporation |
4 / 11 page P4C1299/P4C1299L - ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM Page 4 Document # SRAM144 REV OR TIMIng WAVEFORM OF READ CYCLE nO. 1 (OE COnTROLLED)(5) TIMIng WAVEFORM OF READ CYCLE nO. 2 (ADDRESS COnTROLLED)(5,6) TIMIng WAVEFORM OF READ CYCLE nO. 3 (CE 1,2 COnTROLLED) (5,6) notes: 1. Stresses greater than those listed under MAxIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAxIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with V IL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20ns. 4. This parameter is sampled and not 100% tested. 5. CE 1 and CE2 are LOW and WE is HIGH for READ cycle. 6. WE is HIGH and ADDRESS must be valid prior to, or coincident with CE 1 and CE2 transitions LOW. 7. Transition is measured ± 200 mV from steady state voltage prior to change,withloadingasspecifiedinFigure1. Thisparameterissampled and not 100% tested. 8. Read Cycle Time is measured from the last valid address to the first transitioning address. |
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