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AM1808 Datasheet(PDF) 1 Page - Texas Instruments |
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AM1808 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 262 page AM1808 www.ti.com SPRS653C – FEBRUARY 2010 – REVISED DECEMBER 2011 AM1808 ARM Microprocessor Check for Samples: AM1808 1 AM1808 ARM Microprocessor 1.1 Features 12 • Highlights • Two External Memory Interfaces: – 375/456-MHz ARM926EJ-S™ RISC Core – EMIFA – ARM9 Memory Architecture • NOR (8-/16-Bit-Wide Data) – Programmable Real-Time Unit Subsystem • NAND (8-/16-Bit-Wide Data) – Enhanced Direct-Memory-Access Controller • 16-Bit SDRAM With 128 MB Address 3 (EDMA3) Space – Two External Memory Interfaces – DDR2/Mobile DDR Memory Controller – Three Configurable 16550 type UART • 16-Bit DDR2 SDRAM With 512 MB Modules Address Space or – Two Serial Peripheral Interfaces (SPI) • 16-Bit mDDR SDRAM With 256 MB Address Space – Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO) • Three Configurable 16550 type UART Modules: – Two Master/Slave Inter-Integrated Circuit – With Modem Control Signals – USB 2.0 OTG Port With Integrated PHY – 16-byte FIFO – One Multichannel Audio Serial Port – 16x or 13x Oversampling Option – 10/100 Mb/s Ethernet MAC (EMAC) • LCD Controller – Three 64-Bit General-Purpose Timers • Two Serial Peripheral Interfaces (SPI) Each With Multiple Chip-Selects – One 64-bit General-Purpose/Watchdog Timer • Two Multimedia Card (MMC)/Secure Digital (SD) – TwoEnhanced Pulse Width Modulators Card Interface with Secure Data I/O (SDIO) – Three 32-Bit Enhanced Capture Modules Interfaces • 375/456MHz ARM926EJ-S™ RISC MPU • Two Master/Slave Inter-Integrated Circuit (I2C • ARM926EJ-S Core Bus ™) – 32-Bit and 16-Bit (Thumb®) Instructions • One Host-Port Interface (HPI) With 16-Bit-Wide – Single Cycle MAC Muxed Address/Data Bus For High Bandwidth – ARM® Jazelle® Technology • Programmable Real-Time Unit Subsystem – EmbeddedICE-RT™ for Real-Time Debug (PRUSS) • ARM9 Memory Architecture – Two Independent Programmable Realtime – 16K-Byte Instruction Cache Unit (PRU) Cores – 16K-Byte Data Cache • 32-Bit Load/Store RISC architecture – 8K-Byte RAM (Vector Table) • 4K Byte instruction RAM per core – 64K-Byte ROM • 512 Bytes data RAM per core • Enhanced Direct-Memory-Access Controller 3 • PRU Subsystem (PRUSS) can be disabled (EDMA3): via software to save power – 2 Channel Controllers • Register 30 of each PRU is exported from the subsystem in addition to the normal – 3 Transfer Controllers R31 output of the PRU cores. – 64 Independent DMA Channels – Standard power management mechanism – 16 Quick DMA Channels • Clock gating – Programmable Transfer Burst Size • Entire subsystem under a single PSC • 128K-Byte On-Chip Memory clock gating domain • 1.8V or 3.3V LVCMOS IOs (except for USB and – Dedicated interrupt controller DDR2 interfaces) – Dedicated switched central resource 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to Copyright © 2010–2011, Texas Instruments Incorporated specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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