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PEMD13_PUMD13 Datasheet(PDF) 3 Page - NXP Semiconductors |
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PEMD13_PUMD13 Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 16 page PEMD13_PUMD13 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 7 December 2011 3 of 16 NXP Semiconductors PEMD13; PUMD13 NPN/PNP resistor-equipped transistors; R1 = 4.7 k , R2 = 47 k 5. Limiting values [1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint. [2] Reflow soldering is the only recommended soldering method. Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Per transistor; for the PNP transistor (TR2) with negative polarity VCBO collector-base voltage open emitter - 50 V VCEO collector-emitter voltage open base - 50 V VEBO emitter-base voltage open collector - 5 V VI input voltage TR1 positive - +30 V negative - 5V input voltage TR2 positive - +5 V negative - 30 V IO output current - 100 mA ICM peak collector current single pulse; tp 1ms -100 mA Ptot total power dissipation Tamb 25 C PEMD13 (SOT666) [1][2] -200 mW PUMD13 (SOT363) [1] -200 mW Per device Ptot total power dissipation Tamb 25 C PEMD13 (SOT666) [1][2] -300 mW PUMD13 (SOT363) [1] -300 mW Tj junction temperature - 150 C Tamb ambient temperature 65 +150 C Tstg storage temperature 65 +150 C |
Similar Part No. - PEMD13_PUMD13_15 |
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Similar Description - PEMD13_PUMD13_15 |
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