M2S56D30AKT-75A datasheet(11/37 Pages) MITSUBISHI

Part #	M2S56D30AKT-75A

Description	256M Double Data Rate Synchronous DRAM

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Manufacturer	MITSUBISHI [Mitsubishi Electric Semiconductor]

Direct Link	http://www.mitsubishichips.com

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11

MITSUBISHI ELECTRIC

Jul. '01 Preliminary

MITSUBISHI LSIs

DDR SDRAM (Rev.1.0)

M2S56D20/ 30/ 40AKT

256 M Double Data Rate Synchronous DRAM

FUNCTION TRUTH TABLE for CKE

ABBREVIATIONS:

H=High Level, L=Low Level, X=Don't Care

NOTES:

1. CKE Low to High transition will re-enable CLK and other inputs asynchronously.

A minimum setup time must be satisfied before any command other than EXIT.

2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.

3. Must be legal command.

Current State

CKE n-1

CKE n

/CS

/RAS

/CAS

/WE

Address

Action

Notes

H

X

INVALID

1

L

H

X

Exit Self-Refresh (Idle after tRC)

1

L

H

L

H

X

Exit Self-Refresh (Idle after tRC)

1

L

H

L

H

L

X

ILLEGAL

1

L

H

L

H

L

X

ILLEGAL

1

L

H

L

X

ILLEGAL

1

L

X

NOP (Maintain Self-Refresh)

1

H

X

INVALID

L

H

X

Exit Power Down to Idle

L

X

NOP (Maintain Self-Refresh)

H

X

Refer to Function Truth Table

2

H

L

H

X

Enter Self-Refresh

2

H

L

H

X

Enter Power Down

2

H

L

H

X

Enter Power Down

2

H

L

H

L

X

ILLEGAL

2

H

L

H

L

X

ILLEGAL

2

H

L

X

ILLEGAL

2

L

X

Refer to Current State =Power Down

2

H

X

Refer to Function Truth Table

H

L

X

Begin CLK Suspend at Next Cycle

3

L

H

X

Exit CLK Suspend at Next Cycle

3

L

X

Maintain CLK Suspend

ANY STATE

other than listed

above

SELF-

REFRESHING

POWER

DOWN

ALL BANKS

IDLE

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