![]() |
Electronic Components Datasheet Search |
|
NCP186 Datasheet(PDF) 11 Page - ON Semiconductor |
|
NCP186 Datasheet(HTML) 11 Page - ON Semiconductor |
11 / 13 page ![]() NCP186 www.onsemi.com 11 APPLICATIONS INFORMATION General The NCP186 is a high performance 1 A low dropout linear regulator (LDO) delivering excellent noise and dynamic performance. Thanks to its adaptive ground current behavior the device consumes only 90 mA typ. of quiescent current (no−load condition). The regulator features low noise of 48 mVRMS, PSRR of 75 dB at 1 kHz and very good line/load transient performance. Such excellent dynamic parameters, small dropout voltage and small package size make the device an ideal choice for powering the precision noise sensitive circuitry in portable applications. A logic EN input provides ON/OFF control of the output voltage. When the EN is low the device consumes as low as 100 nA typ. from the IN pin. The device is fully protected in case of output overload, output short circuit condition or overheating, assuring a very robust design. Input Capacitor Selection (CIN) Input capacitor connected as close as possible is necessary to ensure device stability. The X7R or X5R capacitor should be used for reliable performance over temperature range. The value of the input capacitor should be 1 mF or greater for the best dynamic performance. This capacitor will provide a low impedance path for unwanted AC signals or noise modulated onto the input voltage. There is no requirement for the ESR of the input capacitor but it is recommended to use ceramic capacitor for its low ESR and ESL. A good input capacitor will limit the influence of input trace inductance and source resistance during load current changes. Output Capacitor Selection (COUT) The LDO requires an output capacitor connected as close as possible to the output and ground pins. The recommended capacitor value is 1 mF, ceramic X7R or X5R type due to its low capacitance variations over the specified temperature range. The LDO is designed to remain stable with minimum effective capacitance of 0.8 mF. When selecting the capacitor the changes with temperature, DC bias and package size needs to be taken into account. Especially for small package size capacitors such as 0201 the effective capacitance drops rapidly with the applied DC bias voltage (refer the capacitor’s datasheet for details). There is no requirement for the minimum value of equivalent series resistance (ESR) for the COUT but the maximum value of ESR should be less than 0.5 W. Larger capacitance and lower ESR improves the load transient response and high frequency PSRR. Only ceramic capacitors are recommended, the other types like tantalum capacitors not due to their large ESR. Enable Operation The LDO uses the EN pin to enable/disable its operation and to deactivate/activate the output discharge function (A−version only). If the EN pin voltage is < 0.4 V the device is disabled and the pass transistor is turned off so there is no current flow between the IN and OUT pins. On A−version the active discharge transistor is active so the output voltage is pulled to GND through 34 W (typ.) resistor. If the EN pin voltage is > 1.0 V the device is enabled and regulates the output voltage. The active discharge transistor is turned off. The EN pin has internal pull−down current source with value of 150 nA typ. which assures the device is turned off when the EN pin is unconnected. In case when the EN function isn’t required the EN pin should be tied directly to IN pin. Output Current Limit Output current is internally limited to a 1.4 A typ. The LDO will source this current when the output voltage drops down from the nominal output voltage (test condition is VOUT−NOM – 100mV). If the output voltage is shorted to ground, the short circuit protection will limit the output current to 1.4 A typ. The current limit and short circuit protection will work properly over the whole temperature and input voltage ranges. There is no limitation for the short circuit duration. Thermal Shutdown When the LDO’s die temperature exceeds the thermal shutdown threshold value the device is internally disabled. The IC will remain in this state until the die temperature decreases by value called thermal shutdown hysteresis. Once the IC temperature falls this way the LDO is back enabled. The thermal shutdown feature provides the protection against overheating due to some application failure and it is not intended to be used as a normal working function. Power Dissipation Power dissipation caused by voltage drop across the LDO and by the output current flowing through the device needs to be dissipated out from the chip. The maximum power dissipation is dependent on the PCB layout, number of used Cu layers, Cu layers thickness and the ambient temperature. The maximum power dissipation can be computed by following equation: P D(MAX) + T J * TA q JA [W] (eq. 1) Where (TJ − TA) is the temperature difference between the junction and ambient temperatures and θJA is the thermal resistance (dependent on the PCB as mentioned above). |
Similar Part No. - NCP186 |
|
Similar Description - NCP186 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |