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M30622MA-812FP Datasheet(PDF) 10 Page - Mitsubishi Electric Semiconductor |
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M30622MA-812FP Datasheet(HTML) 10 Page - Mitsubishi Electric Semiconductor |
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10 / 184 page  Tentative Specifications REV.A Mitsubishi microcomputers M16C / 62T Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Specifications in this manual are tentative and subject to change. Under development 10 Pin Description Pin Description Pin name P40 to P47 ______ ______ CS0 to CS3, A16 to A19 P50 to P57 ________ ______ WRL/WR, _________ _______ WRH/BHE, RD, BCLK, __________ HLDA, __________ HOLD, ALE, ________ RDY P60 to P67 P70 to P77 P80 to P84, P86, P87, P85 P90 to P97 P100 to P107 Signal name I/O port P4 I/O port P5 I/O port P6 I/O port P7 I/O port P8 I/O port P85 I/O port P9 I/O port P10 I/O type Input/output Output Output Input/output Output Output Output Output Output Input Output Input Input/output Input/output Input/output Input/output Input/output Input Input/output Input/output Function This is an 8-bit I/O port equivalent to P0. ______ ______ _______ _______ These pins output CS0–CS3 signals and A16–A19. CS0–CS3 are chip select signals used to specify an access space. A16–A19 are 4 high-order address bits. This is an 8-bit I/O port equivalent to P0. In single-chip mode, P57 in this port outputs a divide-by-8 or divide-by-32 clock of XIN or a clock of the same frequency as XCIN as selected by software. ________ ________ ______ _______ _____ __________ Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE ________ _________ _______ ______ signals. WRL and WRH, and BHE and WR can be switched using software control. ________ ________ _____ s WRL, WRH, and RD selected With a 16-bit external data bus, data is written to even addresses ________ when the WRL signal is “L” and to the odd addresses when the ________ _____ WRH signal is “L”. Data is read when RD is “L”. ______ _______ _____ s WR, BHE, and RD selected ______ _____ Data is written when WR is “L”. Data is read when RD is “L”. Odd _______ addresses are accessed when BHE is “L”. Use this mode when using an 8-bit external data bus. __________ While the input level at the HOLD pin is “L”, the microcomputer is __________ placed in the hold state. While in the hold state, HLDA outputs a “L” level. ALE is used to latch the address. While the input level of _______ the RDY pin is “L”, the microcomputer is in the ready state. This is an 8-bit I/O port equivalent to P0. Pins in this port also function as UART0 and UART1 I/O pins as selected by software. This is an 8-bit I/O port equivalent to P0 (P70 and P71 are N channel open-drain output). Pins in this port also function as timer A0–A3, timer B5 or UART2 I/O pins as selected by software. P80 to P84, P86 and P87 are I/O ports with the same functions as P0. Using software, they can be made to function as the I/O pins for timer A4 and the input pins for external interrupts. P86 and P87 can be set using software to function as the I/O pins for a sub clock generation circuit. In this case, connect a quartz oscillator between P86 (XCOUT pin) and P87 (XCIN pin). P85 is an input-only port that _______ _______ also functions for NMI. The NMI interrupt is generated when the _______ input at this pin changes from “H” to “L”. The NMI function cannot be cancelled using software. The pull-up cannot be set for this pin. This is an 8-bit I/O port equivalent to P0. Pins in this port also function as SI/O 3, 4 I/O pins, timer B0–B4 input pins, D-A converter output pins, A-D converter extended input pins, or A-D trigger input pins as selected by software. This is an 8-bit I/O port equivalent to P0. Pins in this port also funciton as A-D converter input pins. Furthermore, P104–P107 also function as input pins for the key input interrupt function. Note 1: In M30623(80-pin package), the following signals do not have the corresponding external pin. _______ _______ q P10/D8 to P14/D12, P15/D13/INT3 to P17/D15/INT5 _______ _______ q P44/CS0 to P47/CS3 ________ ________ __ ___ q P72/CLK2/TA1OUT/V, P73/CST2/RTS2/TA1IN/V, P74/TA2OUT/W, P75/TA2IN/W q P91/TB1IN/SIN3 Note 2: The M16C/62T group is not guaranteed to operate in memory expansion and microprocessor modes. |
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