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MAX1002CAX Datasheet(PDF) 3 Page - Maxim Integrated Products

Part # MAX1002CAX
Description  Low-Power, 60Msps, Dual, 6-Bit ADC
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX1002CAX Datasheet(HTML) 3 Page - Maxim Integrated Products

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Low-Power, 60Msps, Dual, 6-Bit ADC
_______________________________________________________________________________________
3
AC ELECTRICAL CHARACTERISTICS
(VCC, VCCO = +5V ±5%; TA = +25°C; unless otherwise noted.)
Note 1: Best straight-line linearity method.
Note 2: A typical application will AC couple the analog input to the DC bias level present at the analog inputs (typically 2.35V).
However, it is also possible to DC couple the analog input (using differential or single-ended drive) within this common-
mode input range (Figures 4, 5).
Note 3: PSSR is defined as the change in the mid-gain, full-scale range as a function of the variation in VCC supply voltage
(expressed in decibels).
Note 4: The current in the VCCO supply is a strong function of the capacitive loading on the digital outputs. To minimize supply
transients and achieve the best dynamic performance, reduce the capacitive loading effects by keeping line lengths on the
digital outputs to a minimum.
Note 5: Offset-correction compensation enabled, 0.22µF at Q and I compensation inputs (Figures 2, 3).
Note 6: tPD and tSKEW are measured from the 1.4V level of the output clock, to the 1.4V level of either the rising or falling edge of a
data bit. tDCLK is measured from the 50% level of the clock overdrive signal on TNK+ to the 1.4V level of DCLK. The capac-
itive load on the outputs is 15pF.
Gain = GND, open, VCC
GAIN = open (mid gain),
VIN = 50MHz, -1dB below FS
GAIN = open (mid gain)
5.7
ENOBM
5.6
5.85
Effective Number of Bits
Gain = open (mid gain)
Gain = VCC (low gain)
Q channel
I channel
dB
CONDITIONS
MHz
55
BW
Analog Input -0.5dB Bandwidth
Msps
60
fMAX
Maximum Sample Rate
-55
XTLK
Gain = VCC (high gain)
Crosstalk Between ADCs
LSB
-0.5
0.5
OFF
Input Offset (Note 5)
-0.5
0.5
dB
35.4
37
SINAD
Signal-to-Noise and Distortion
Ratio
Bits
5.85
ENOBL
5.8
ENOBH
(Note 5)
dB
-0.2
±0.1
0.2
AM
Amplitude Match Between
ADCs
LSB
-0.5
±0.25
0.5
OMM2
Offset Mismatch Between ADCs
(Note 6)
(Note 6)
ns
3.6
tSKEW
Data Valid Skew
ns
7.1
tPD
DCLK to Data-Propagation
Delay
degrees
-2
±0.5
2
PM
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Phase Match Between ADCs
TNK+ to DCLK (Note 6)
ns
5.3
tDCLK
Input to DCLK Delay
ns
5.5
tAP
Aperture Delay
clock
cycle
1
PD
Pipeline Delay
DYNAMIC PERFORMANCE (GAIN = open; external 60MHz clock (Figure 7); VINI, VINIQ = 20MHz sine; amplitude -1dB below FS;
unless otherwise noted.)
TIMING CHARACTERISTICS (data outputs: RL = 1MΩ, CL = 15pF, Figure 8)


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