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MAX1080 Datasheet(PDF) 11 Page - Maxim Integrated Products |
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MAX1080 Datasheet(HTML) 11 Page - Maxim Integrated Products |
11 / 24 page Detailed Description The MAX1080/MAX1081 ADCs use a successive- approximation conversion technique and input T/H cir- cuitry to convert an analog signal to a 10-bit digital out- put. A flexible serial interface provides easy interface to microprocessors (µPs). Figure 3 shows a functional dia- gram of the MAX1080/MAX1081. Pseudo-Differential Input The equivalent circuit of Figure 4 shows the MAX1080/ MAX1081s’ input architecture, which is composed of a T/H, input multiplexer, input comparator, switched- capacitor DAC, and reference. In single-ended mode, the positive input (IN+) is con- nected to the selected input channel and the negative input (IN-) is set to COM. In differential mode, IN+ and IN- are selected from the following pairs: CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Configure the channels according to Tables 1 and 2. The MAX1080/MAX1081 input configuration is pseudo- differential because only the signal at IN+ is sampled. The return side (IN-) is connected to the sampling capacitor while converting and must remain stable within ±0.5LSB (±0.1LSB for best results) with respect to GND during a conversion. If a varying signal is applied to the selected IN-, its amplitude and frequency must be limited to maintain accuracy. The following equations express the relation- ship between the maximum signal amplitude and its frequency to maintain ±0.5LSB accuracy. Assuming a sinusoidal signal at IN-, the input voltage is determined by: The maximum voltage variation is determined by: A 2.6Vp-p, 60Hz signal at IN- will generate a ±0.5LSB error when using a +2.5V reference voltage and a 2.5µs conversion time (15 / fSCLK). When a DC refer- ence voltage is used at IN-, connect a 0.1µF capacitor to GND to minimize noise at the input. During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor CHOLD. The acquisition interval spans three SCLK cycles and ends on the falling SCLK edge after the input control word’s last bit has been entered. At the end of the acquisition interval, the T/H switch opens, retaining charge on CHOLD as a sample of the signal at IN+. The conver- sion interval begins with the input multiplexer switching CHOLD from IN+ to IN-. This unbalances node ZERO at the comparator’s input. The capacitive DAC adjusts during the remainder of the conversion cycle to restore node ZERO to VDD1/2 within the limits of 10-bit resolu- tion. This action is equivalent to transferring a 12pF ✕ [(VIN+ - VIN-)] charge from CHOLD to the binary- weighted capacitive DAC, which in turn forms a digital representation of the analog input signal. max d dt V2 f 1LSB t V 2t IN IN CONV REF 10 CONV ν π − − = () ≤= 300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference ______________________________________________________________________________________ 11 INPUT SHIFT REGISTER CONTROL LOGIC INT CLOCK OUTPUT SHIFT REGISTER +1.22V REFERENCE T/H ANALOG INPUT MUX 10 + 2-BIT SAR ADC IN DOUT SSTRB VDD1 VDD2 GND SCLK DIN COM REFADJ REF OUT REF CLOCK +2.500V 17k 10 11 12 9 14 15 16 17 18 CH6 7 CH7 8 CH4 5 CH5 6 CH1 2 CH2 3 CH3 4 CH0 1 MAX1080 MAX1081 CS SHDN 20 19 13 2.05 A ≈ Figure 3. Functional Diagram CHOLD 12pF RIN 800 Ω HOLD INPUT MUX CSWITCH* *INCLUDES ALL INPUT PARASITICS SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM. PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7. AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL. CH0 REF GND CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM ZERO VDD1/2 COMPARATOR CAPACITIVE DAC 6pF TRACK Figure 4. Equivalent Input Circuit νπ IN IN V sin(2 ft) −− = () |
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