high-frequency components may be aliased into the

frequency band of interest. Minimize noise by present-

ing a low impedance (at the frequencies contained in

the noise signal) at the inputs. This requires bypassing

AIN to AGND, or buffering the input with an amplifier

that has a small-signal bandwidth of several MHz, or

preferably both. AIN has about 4MHz of bandwidth.

Distortion

Avoid degrading dynamic performance by choosing an

amplifier with distortion much less than the MAX1062’s

total harmonic distortion (THD = -99dB at 1kHz) at fre-

quencies of interest. If the chosen amplifier has insuffi-

cient common-mode rejection, which results in

degraded THD performance, use the inverting configu-

ration (positive input grounded) to eliminate errors from

this source. Low temperature-coefficient, gain-setting

resistors reduce linearity errors caused by resistance

changes due to self-heating. To reduce linearity errors

due to finite amplifier gain, use amplifier circuits with

sufficient loop gain at the frequencies of interest.

DC Accuracy

To improve DC accuracy, choose a buffer with an offset

much less than the MAX1062’s offset (1mV (max) for +5V

supply), or whose offset can be trimmed while maintain-

ing stability over the required temperature range.

Serial Interfaces

The MAX1062’s interface is fully compatible with SPI,

QSPI, and MICROWIRE standard serial interfaces.

If a serial interface is available, establish the CPU’s ser-

ial interface as master, so that the CPU generates the

serial clock for the MAX1062. Select a clock frequency

between 100kHz and 4.8MHz:

1) Use a general-purpose I/O line on the CPU to pull

CS low.

2) Activate SCLK for a minimum of 24 clock cycles.

The serial data stream of eight leading zeros fol-

lowed by the MSB of the conversion result begins at

the falling edge of CS. DOUT transitions on SCLK’s

falling edge and the output is available in MSB-first

14-Bit, +5V, 200ksps ADC with 10µA Shutdown

______________________________________________________________________________________

11

A0

A1

CLK

CHANGE MUX INPUT HERE

CONVERSION

IN1

A0

A1

IN2

IN3

IN4

OUT

ACQUISITION

4-TO-1

MUX

AIN

CS

MAX1062

CS

Figure 9. Change Multiplexer Input Near Beginning of Conversion to Allow Time for Slewing and Settling