Read Mode (MODE = 0)

In read mode, conversions and data access are con-

trolled by the

RD input (Figure 3). The comparator

inputs track the analog input voltage for the duration of

low. With µPs that can be forced into a wait state, hold

RD low until output data appears. The µP starts the

conversion, waits, and then reads data with a single

read instruction.

In read mode,

WR/RDY is configured as a status output

(RDY), so it can drive the ready or wait input of a µP.

RDY is an open-collector output (no internal pull-up)

that goes low after the falling edge of

CS and goes high

at the end of the conversion. If not used, the

WR/RDY

pin can be left unconnected. The

INT output goes low

at the end of the conversion and returns high on the ris-

ing edge of

CS or RD.

Write-Read Mode (MODE = 1)

Figures 4 and 5 show the operating sequence for write-

read mode. The comparator inputs track the analog

initiated by a falling edge of

WR. When WR returns

high, the result of the four-MSBs flash is latched into the

output buffers and the conversion of the four-LSBs flash

starts.

INT goes low, indicating conversion end, and the

lower four data bits are latched into the output buffers.

The data is then accessible after

RD goes low (see

Timing Characteristics).

going low to the start of another conversion (

WR going

low).

Options for reading data from the converter include

using internal delay, reading before delay, and pipelined

operation (discussed in the following sections).

Using Internal Delay

The µP waits for the

INT output to go low before reading

the data (Figure 4).

INT goes low after the rising edge of

WR, indicating that the conversion is complete and the

result is available in the output latch. With

CS low, data

outputs D0–D7 can be accessed by pulling

RD low. INT

is then reset by the rising edge of

CS or RD.

Fastest Conversion:

Reading Before Delay

An external method of controlling the conversion time is

shown in Figure 5. The internally generated delay

age, and can be overridden with

RD to achieve the

fastest conversion time.

RD is brought low after the ris-

ing edge of

WR, but before INT goes low. This com-

pletes the conversion and enables the output buffers

+3V, 400ksps, 4/8-Channel,

8-Bit ADCs with 1µA Power-Down

8

_______________________________________________________________________________________

WITH EXTERNAL

PULL-UP

D0–D7

RDY

RD

CS

PWRDN

INT

A0–A2

VALID DATA

(N)

ADDRESS VALID (N + 1)

ADDRESS VALID

(N)

D0–D7

RD

WR

CS

INT

VALID DATA

(N)

A0–A2

ADDRESS

VALID (N)

ADDRESS VALID (N + 1)

Figure 3. Read Mode Timing (Mode = 0)

RD

WR

CS

INT

VALID DATA

(N)

A0–A2

D0–D7

ADDRESS

VALID (N)

ADDRESS VALID (N + 1)