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F59D4G81A Datasheet(PDF) 11 Page - Elite Semiconductor Memory Technology Inc. |
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F59D4G81A Datasheet(HTML) 11 Page - Elite Semiconductor Memory Technology Inc. |
11 / 54 page ESMT F59D4G81A / F59D4G161A Elite Semiconductor Memory Technology Inc. Publication Date: May 2014 Revision: 1.4 11/54 NAND Flash Technical Notes Mask Out Initial Invalid Block(s) Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by ESMT. The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 4bit/512Byte (4bit/256Word) ECC. Identifying Initial Invalid Block(s) and Block Replacement Management All device locations are erased (FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial invalid block(s) status is defined by the 1st byte in the spare area. ESMT makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at the 1st byte column address in the spare area. Do not erase or program factory-marked bad blocks. The host controller must be able to recognize the initial invalid block information and to create a corresponding table to manage block replacement upon erase or program error when additional invalid blocks develop with Flash memory usage. |
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