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F59L1G81A Datasheet(PDF) 7 Page - Elite Semiconductor Memory Technology Inc. |
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F59L1G81A Datasheet(HTML) 7 Page - Elite Semiconductor Memory Technology Inc. |
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7 / 35 page  ESMT F59L1G81A Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2013 Revision: 1.2 7/35 AC TEST CONDITION (TA=0 to 70 , V ℃ CC=2.7V~3.6V, unless otherwise noted) Parameter Condition Input Pulse Levels 0V to VCC Input Rise and Fall Times 5 ns Input and Output Timing Levels VCC /2 Output Load 1 TTL Gate and CL=50pF CAPACITANCE (TA=25 , V ℃ CC=3.3V, f=1.0MHz) Item Symbol Test Condition Min. Max. Unit Input / Output Capacitance CI/O VIL = 0V - 8 pF Input Capacitance CIN VIN = 0V - 8 pF Note: Capacitance is periodically sampled and not 100% tested. MODE SELECTION CLE ALE CE WE RE WP Mode H L L Rising H X Command Input L H L Rising H X Read Mode Address Input (4 clock) H L L Rising H H Command Input L H L Rising H H Write Mode Address Input (4 clock) L L L Rising H H Data Input L L L H Falling X Data Output X X X X H X During Read (Busy) X X X X X H During Program (Busy) X X X X X H During Erase (Busy) X X (1) X X X L Write Protect X X H X X 0V/VCC (2) Stand-by Note: 1. X can be VIL or VIH. 2. WP should be biased to CMOS high or CMOS low for stand-by. Program / Erase Characteristics Parameter Symbol Min. Typ. Max. Unit Program Time tPROG (1) - 200 700 us Dummy Busy Time for Cache Program tCBSY (2) - 3 700 us Number of Partial Program Cycles in the Same Page NOP - - 4 Cycle Block Erase Time tBERS - 1.5 10 ms Note: 1. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3V VCC and 25℃ temperature. 2. Max. time of tCBSY depends on timing between internal program completion and data in. |
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