ESMT

M12L32321A (2G)

Elite Semiconductor Memory Technology Inc.

Publication Date : Jul. 2012

Revision : 1.0

8/28

Burst Length and Sequence

(Burst of Two)

Starting Address

(column address A0 binary)

Sequential Addressing

Sequence (decimal)

Interleave Addressing

Sequence (decimal)

0

0,1

0,1

1

1,0

1,0

(Burst of Four)

Starting Address

(column address A1-A0, binary)

Sequential Addressing

Sequence (decimal)

Interleave Addressing

Sequence (decimal)

00

0,1,2, 3

0,1,2, 3

01

1,2,3, 0

1,0,3, 2

10

2,3,0, 1

2,3,0, 1

11

3,0,1, 2

3,2,1, 0

(Burst of Eight)

Starting Address

(column address A2-A0, binary)

Sequential Addressing

Sequence (decimal)

Interleave Addressing

Sequence (decimal)

000

0,1,2, 3,4, 5,6,7

0,1,2, 3,4, 5,6,7

001

1,2,3, 4,5, 6,7,0

1,0,3, 2,5, 4,7,6

010

2,3,4, 5,6, 7,0,1

2,3,0, 1,6, 7,4,5

011

3,4,5, 6,7, 0,1, 2

3,2,1, 0,7, 6,5,4

100

4,5,6, 7,0, 1,2,3

4,5,6, 7,0, 1,2,3

101

5,6,7, 0,1, 2,3,4

5,4,7, 6,1, 0,3,2

110

6,7,0, 1,2, 3,4, 5

6,7,4, 5,2, 3,0,1

111

7,0,1, 2,3, 4,5, 6

7,6,5, 4,3, 2,1,0

Full page burst is an extension of the above tables of Sequential Addressing, with the length being 256 for device.

POWER UP SEQUENCE

1.Apply power and start clock, attempt to maintain CKE= “H”, DQM = “H” and the other pin are NOP condition at the inputs.

2.Maintain stable power, stable clock and NOP input condition for a minimum of 200us.

3.Issue precharge commands for all banks of the devices.

4.Issue 2 or more auto-refresh commands.

5.Issue mode register set command to initialize the mode register.

Cf.)Sequence of 4 & 5 is regardless of the order.

The device is now ready for normal operation.