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M53D128324A-2E Datasheet(PDF) 1 Page - Elite Semiconductor Memory Technology Inc.

Part # M53D128324A-2E
Description  Bi-directional data strobe (DQS)
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Manufacturer  ESMT [Elite Semiconductor Memory Technology Inc.]
Direct Link  http://www.esmt.com.tw/index.asp
Logo ESMT - Elite Semiconductor Memory Technology Inc.

M53D128324A-2E Datasheet(HTML) 1 Page - Elite Semiconductor Memory Technology Inc.

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ESMT
M53D128324A (2E)
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2012
Revision : 1.0
1/47
DM
DQ
Mode Register &
Extended Mode
Register
Column
Address
Buffer
&
Refresh
Counter
Row
Address
Buffer
&
Refresh
Counter
Sense Amplifier
Column Decoder
Data Control Circuit
Address
Clock
Generator
CLK
CLK
CKE
CS
RAS
CAS
WE
DQS
Mobile DDR SDRAM
1M x 32 Bit x 4 Banks
Mobile DDR SDRAM
Features
JEDEC Standard
Internal pipelined double-data-rate architecture, two data
access per clock cycle
Bi-directional data strobe (DQS)
No DLL; CLK to DQS is not synchronized.
Differential clock inputs (CLK and CLK )
Four bank operation
CAS Latency : 2, 3
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8, 16
Special function support
-
PASR (Partial Array Self Refresh)
-
Internal TCSR (Temperature Compensated Self
Refresh)
-
DS (Drive Strength)
All inputs except data & DM are sampled at the rising
edge of the system clock(CLK)
DQS is edge-aligned with data for READ; center-aligned
with data for WRITE
Data mask (DM) for write masking only
VDD/VDDQ = 1.7V ~ 1.95V
Auto & Self refresh
15.6us refresh interval (64ms refresh period, 4K cycle)
LVCMOS-compatible inputs
Ordering Information
Product ID
Max Freq.
VDD
Package
Comments
M53D128324A -5BG2E
200MHz
M53D128324A -6BG2E
166MHz
M53D128324A -7.5BG2E
133MHz
1.8V
144 ball FBGA
Pb-free
Functional Block Diagram
Bank A
Bank D
Bank B
Bank C


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