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M53D256328A-2F Datasheet(PDF) 5 Page - Elite Semiconductor Memory Technology Inc.

Part # M53D256328A-2F
Description  Internal pipelined double-data-rate architecture, two data
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Manufacturer  ESMT [Elite Semiconductor Memory Technology Inc.]
Direct Link  http://www.esmt.com.tw/index.asp
Logo ESMT - Elite Semiconductor Memory Technology Inc.

M53D256328A-2F Datasheet(HTML) 5 Page - Elite Semiconductor Memory Technology Inc.

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ESMT
M53D256328A (2F)
Elite Semiconductor Memory Technology Inc.
Publication Date :Feb. 2014
Revision : 1.0
5/47
TCSR range
45
75
C
°
Full array
650
700
μ
A
1/2 array
600
650
μ
A
1/4 array
550
600
μ
A
1/8 array
500
550
μ
A
Self Refresh Current
IDD6
CKE = LOW, CLK = LOW,
CLK = HIGH; EMRS set to all
0’s; address & control & data bus
inputs are STABLE
1/16 array
450
500
μ
A
Deep Power Down
Current
IDD8
address & control & data inputs are STABLE
10
μ
A
Note: 1. Input slew rate is 1V/ns.
2. IDD specifications are tested after the device is properly initialized.
3. Definitions for IDD: LOW is defined as V IN ≤ 0.1 * V DDQ;
HIGH is defined as V IN ≥ 0.9 * V DDQ;
STABLE is defined as inputs stable at a HIGH or LOW level;
SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once
per two clock cycles;
- data bus inputs: DQ changing between HIGH and LOW once per clock
cycle; DM and DQS are STABLE.
AC Operation Conditions & Timing Specification
AC Operation Conditions
Parameter
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIHD(AC)
0.8 x VDDQ
VDDQ+0.3
V
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
VILD(AC)
-0.3
0.2 x VDDQ
V
Input Differential Voltage, CLK and CLK inputs
VID(AC)
0.6 x VDDQ
VDDQ+0.6
V
1
Input Crossing Point Voltage, CLK and CLK inputs
VIX(AC)
0.4 x VDDQ
0.6 x VDDQ
V
2
Note: 1. VID is the magnitude of the difference between the input level on CLK and the input on CLK .
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the
same.
Input / Output Capacitance
(VDD = 1.8V, VDDQ =1.8V, TA = 25 C
° , f = 1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance
(A0~A11, BA0~BA1, CKE, CS , RAS , CAS , WE )
CIN1
2
5
pF
Input capacitance (CLK, CLK )
CIN2
4
7
pF
Data & DQS input/output capacitance
COUT
2
7
pF
Input capacitance (DM)
CIN3
2
6
pF


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