+2.7V, Low-Power,

12-Bit Serial ADCs in 8-Pin SO

_______________________________________________________________________________________

7

_______________________________________________________________________Pin Description

6

DOUT

Serial Data Output. Data changes state at SCLK’s falling edge. DOUT is high impedance when CS is

high.

8

SCLK

3

SHDN

Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1240/MAX1241 down to 15µA (max)

supply current. Both the MAX1240 and MAX1241 are fully operational with either SHDN high or float-

ing. For the MAX1240, pulling SHDN high enables the internal reference, and letting SHDN float dis-

ables the internal reference and allows for the use of an external reference.

4

REF

Reference Voltage for Analog-to-Digital Conversion. Internal 2.5V reference output for MAX1240;

bypass with 4.7µF capacitor. External reference voltage input for MAX1241, or for MAX1240 with the

internal reference disabled. Bypass REF with a minimum of 0.1µF when using an external reference.

7

CS

Active-Low Chip Select initiates conversions on the falling edge. When CS is high, DOUT is high

impedance.

5

GND

Analog and Digital Ground

2

AIN

NAME

FUNCTION

1

Positive Supply Voltage: 2.7V to 3.6V, (MAX1240); 2.7 to 5.25V (MAX1241)

PIN

Serial Clock Input. SCLK clocks data out at rates up to 2.1MHz.

0.6

INTEGRAL NONLINEARITY

vs. CODE

-0.6

0

-0.2

-0.4

0.4

0.2

CODE

1024

2048

3072

4096

0

20

-140

0

37.50

FFT PLOT

-120

0

-80

-100

-40

-20

-60

18.75

FREQUENCY (kHz)

____________________________Typical Operating Characteristics (continued)