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MAX1280 Datasheet(PDF) 10 Page - Maxim Integrated Products |
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MAX1280 Datasheet(HTML) 10 Page - Maxim Integrated Products |
10 / 24 page 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference 10 ______________________________________________________________________________________ Pin Description Positive Supply Voltage VDD2 19 Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to VDD1. REFADJ 12 Serial Strobe Output. SSTRB pulses high for one clock period before the MSB decision. High imped- ance when CS is high. SSTRB 15 Serial Data Input. Data is clocked in at SCLK’s rising edge. DIN 16 Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT and SSTRB are high impedance. CS 17 Serial Clock Input. Clocks data in and out of the serial interface and sets the conversion speed. (Duty cycle must be 40% to 60%.) SCLK 18 Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In internal reference mode, the reference buffer provides a +2.500V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to VDD1. REF 11 Analog and Digital Ground GND 13 Serial Data Output. Data is clocked out at SCLK’s rising edge. High impedance when CS is high. DOUT 14 Active-Low Shutdown Input. Pulling SHDN low shuts down the device, reducing supply current to 2µA (typ). SHDN 10 Ground Reference for Analog Inputs. COM sets zero-code voltage in single-ended mode. Must be stable to ±0.5LSB. COM 9 PIN Sampling Analog Inputs CH0–CH7 1–8 FUNCTION NAME VDD2 6k GND DOUT CLOAD 20pF CLOAD 20pF GND 6k DOUT a) High-Z to VOH and VOL to VOH b) High-Z to VOL and VOH to VOL VDD2 6k GND DOUT CLOAD 20pF CLOAD 20pF GND 6k DOUT a) VOH to High-Z b) VOL to High-Z Figure 1. Load Circuits for Enable Time Figure 2. Load Circuits for Disable Time Positive Supply Voltage VDD1 20 |
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Similar Description - MAX1280 |
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