400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,

Serial 12-Bit ADCs with Internal Reference

10

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Pin Description

Positive Supply Voltage

19

REFADJ

12

Serial Strobe Output. SSTRB pulses high for one clock period before the MSB decision. High imped-

ance when CS is high.

SSTRB

15

Serial Data Input. Data is clocked in at SCLK’s rising edge.

DIN

16

Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT

and SSTRB are high impedance.

CS

17

Serial Clock Input. Clocks data in and out of the serial interface and sets the conversion speed. (Duty

cycle must be 40% to 60%.)

SCLK

18

Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.

In internal reference mode, the reference buffer provides a +2.500V nominal output, externally

adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to

REF

11

Analog and Digital Ground

GND

13

Serial Data Output. Data is clocked out at SCLK’s rising edge. High impedance when CS is high.

DOUT

14

Active-Low Shutdown Input. Pulling SHDN low shuts down the device, reducing supply current to 2µA

(typ).

SHDN

10

Ground Reference for Analog Inputs. COM sets zero-code voltage in single-ended mode. Must be

stable to ±0.5LSB.

COM

9

PIN

Sampling Analog Inputs

CH0–CH7

1–8

FUNCTION

NAME

6k

GND

DOUT

20pF

20pF

GND

6k

DOUT

6k

GND

DOUT

20pF

20pF

GND

6k

DOUT

Figure 1. Load Circuits for Enable Time

Figure 2. Load Circuits for Disable Time

Positive Supply Voltage

20