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MAX126BCAX Datasheet(PDF) 10 Page - Maxim Integrated Products |
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MAX126BCAX Datasheet(HTML) 10 Page - Maxim Integrated Products |
10 / 16 page plest software interface requires only three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the ADC, and two more 8-bit transfers to clock out the 10-bit conversion result). See Figure 19 for MAX1248/ MAX1249 QSPI connections. Simple Software Interface Make sure the CPU’s serial interface runs in master mode so the CPU generates the serial clock. Choose a clock frequency from 100kHz to 2MHz. 1) Set up the control byte for external clock mode and call it TB1. TB1 should be of the format: 1XXXXX11 binary, where the Xs denote the particular channel and conversion mode selected. 2) Use a general-purpose I/O line on the CPU to pull CS low. 3) Transmit TB1 and, simultaneously, receive a byte and call it RB1. Ignore RB1. 4) Transmit a byte of all zeros ($00 hex) and, simulta- neously, receive byte RB2. 5) Transmit a byte of all zeros ($00 hex) and, simulta- neously, receive byte RB3. 6) Pull CS high. Figure 5 shows the timing for this sequence. Bytes RB2 and RB3 contain the result of the conversion padded with one leading zero, two sub-bits, and three trailing zeros. The total conversion time is a function of the serial-clock frequency and the amount of idle time between 8-bit transfers. To avoid excessive T/H droop, make sure the total conversion time does not exceed 120µs. Digital Output In unipolar input mode, the output is straight binary (Figure 16). For bipolar inputs, the output is two’s com- plement (Figure 17). Data is clocked out at the falling edge of SCLK in MSB-first format. Clock Modes The MAX1248/MAX1249 may use either an external serial clock or the internal clock to perform the succes- sive-approximation conversion. In both clock modes, the external clock shifts data in and out of the MAX1248/MAX1249. The T/H acquires the input signal as the last three bits of the control byte are clocked into DIN. Bits PD1 and PD0 of the control byte program the clock mode. Figures 6–9 show the timing characteristics common to both modes. External Clock In external clock mode, the external clock not only shifts data in and out, it also drives the analog-to-digital con- version steps. SSTRB pulses high for one clock period after the last bit of the control byte. Successive-approxi- mation bit decisions are made and appear at DOUT on each of the next 10 SCLK falling edges (Figure 5). SSTRB and DOUT go into a high-impedance state when +2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 10 ______________________________________________________________________________________ SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 COM 0 0 1 + – 1 0 1 + – 0 1 0 + – 1 1 0 + – Table 2. Channel Selection in Single-Ended Mode (SGL/ D DIIF F = 1) SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 0 0 1 + – 0 1 0 + – 1 0 1 – + 1 1 0 – + Table 3. Channel Selection in Differential Mode (SGL/ D DIIF F = 0) |
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