+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

8

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NAME

FUNCTION

1

Positive Supply Voltage

2–5

CH0–CH3

Sampling Analog Inputs

PIN

6

COM

Ground reference for analog inputs. COM sets zero-code voltage in single-ended mode. Must be

stable to ±0.5LSB.

7

SHDN

Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1246/MAX1247 down; otherwise, they

are fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compensation

mode. Letting SHDN float puts the reference-buffer amplifier in external compensation mode.

12

DOUT

Serial Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.

11

DGND

Digital Ground

10

AGND

Analog Ground

8

VREF

Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.

In internal reference mode (MAX1246 only), the reference buffer provides a 2.500V nominal output,

externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling

16

SCLK

Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets

the conversion speed. (Duty cycle must be 40% to 60%.)

15

CS

Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is

high impedance.

14

DIN

Serial Data Input. Data is clocked in at SCLK’s rising edge.

13

SSTRB

Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX1246/MAX1247 begin the

A/D conversion, and goes high when the conversion is finished. In external clock mode, SSTRB pulses

high for one clock period before the MSB decision. High impedance when CS is high (external clock

mode).

______________________________________________________________Pin Description

6k

DGND

DOUT

50pF

50pF

DGND

6k

DOUT

6k

DGND

DOUT

50pF

50pF

DGND

6k

DOUT

Figure 1. Load Circuits for Enable Time

Figure 2. Load Circuits for Disable Time

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REFADJ