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MAX1239MEEE Datasheet(PDF) 6 Page - Maxim Integrated Products

Part # MAX1239MEEE
Description  2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX1239MEEE Datasheet(HTML) 6 Page - Maxim Integrated Products

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2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
6
_______________________________________________________________________________________
Typical Operating Characteristics
(VDD = 3.3V (MAX1237/MAX1239), VDD = 5V (MAX1236/MAX1238), fSCL = 1.7MHz, (50% duty cycle), fSAMPLE = 94.4ksps, single-
ended, unipolar, TA = +25°C, unless otherwise noted.)
-0.5
-0.2
-0.4
-0.3
0.2
0.1
0.1
0
0.3
0.5
0
4000
DIFFERENTIAL NONLINEARITY
vs. DIGITAL CODE
DIGITAL OUTPUT CODE
1000 1500
500
2000 2500 3000 3500
0.4
-1.0
-0.4
-0.6
-0.8
-0.2
0
0.2
0.4
0.6
0.8
1.0
INTEGRAL NONLINEARITY
vs. DIGITAL CODE
DIGITAL OUTPUT CODE
0
4000
1000 1500
500
2000 2500 3000 3500
-180
-160
-140
-120
-100
-80
-60
0
10k
20k
30k
40k
50k
FFT PLOT
FREQUENCY (Hz)
fSAMPLE = 94.4ksps
fIN = 10kHz
300
400
350
500
450
600
550
650
750
700
800
-40
-10
5
-25
20
35
50
65
80
SUPPLY CURRENT vs. TEMPERATURE
(MAX1238/MAX1239)
TEMPERATURE (
°C)
INTERNAL REFERENCE MAX1239/MAX1237
INTERNAL REFERENCE MAX1238/MAX1236
EXTERNAL REFERENCE MAX1238/MAX1236
EXTERNAL REFERENCE MAX1239/MAX1237
SETUP BYTE
EXT REF: 10111011
INT REF: 11011011
0
0.2
0.1
0.4
0.3
0.5
0.6
2.7
5.2
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
INPUT VOLTAGE (V)
3.7
3.2
4.2
4.7
SDA = SCL = VDD
0
0.10
0.05
0.20
0.15
0.30
0.25
0.35
0.45
0.40
0.50
-40
-10
5
-25
20
35
50
65
80
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
TEMPERATURE (
°C)
MAX1238
MAX1239
and for the MAX1236/MAX1238 where N is the number of bits and VREF.
Note 10: A master device must provide a data hold time for SDA (referred to VIL of SCL) in order to bridge the undefined region of
SCL’s falling edge (see Figure 1).
Note 11: CB = total capacitance of one bus line in pF.
Note 12: fSCL must meet the minimum clock low time plus the rise/fall times.
VV
VV
V
VV
FS
FS
REF
N
(.
)
( .
)
(.
.
)
55
45
21
55
45
[] ×
TIMING CHARACTERISTICS (Figure 1) (continued)
(VDD = 2.7V to 3.6V (MAX1237/MAX1239), VDD = 4.5V to 5.5V (MAX1236/MAX1238), VREF = 2.048V (MAX1237/MAX1239), VREF =
4.096V (MAX1236/MAX1238), CREF = 0.1µF, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C, see Tables 1–5 for programming notation.)


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