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MAX1297AEEG Datasheet(PDF) 9 Page - Maxim Integrated Products |
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MAX1297AEEG Datasheet(HTML) 9 Page - Maxim Integrated Products |
9 / 20 page 265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface _______________________________________________________________________________________ 9 BIT PD1, PD0 0 D7, D6 PD1 and PD0 select the various clock and power-down modes. Full Power-Down Mode. Clock mode is unaffected. D5 ACQMOD ACQMOD = 0: Internal Acquisition Mode ACQMOD = 1: External Acquisition Mode NAME FUNCTIONAL DESCRIPTION 0 1 0 Standby Power-Down Mode. Clock mode is unaffected. 0 1 1 Normal Operation Mode. External clock mode selected. 1 Normal Operation Mode. Internal clock mode selected. D4 SGL/DIF SGL/DIF = 0: Pseudo-Differential Analog Input Mode SGL/DIF = 1: Single-Ended Analog Input Mode In single-ended mode, input signals are referred to COM. In differential mode, the voltage difference between two channels is measured (Tables 2, 4). D3 UNI/BIP UNI/BIP = 0: Bipolar Mode UNI/BIP = 1: Unipolar Mode In unipolar mode, an analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range from -VREF/2 to +VREF/2. D2, D1, D0 A2, A1, A0 Address bits A2, A1, A0 select which of the 6/2 (MAX1295/MAX1297) channels is to be converted (Tables 2, 3). Table 1. Control-Byte Functional Description the analog inputs. This configuration is pseudo-differ- ential in that only the signal at IN+ is sampled. The return side (IN-) must remain stable within ±0.5LSB (±0.1LSB for best performance) with respect to GND during a conversion. To accomplish this, connect a 0.1µF capacitor from IN- (the selected input) to GND. During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor CHOLD. At the end of the acquisition interval, the T/H switch opens, retaining charge on CHOLD as a sample of the signal at IN+. The conversion interval begins with the input multiplex- er switching CHOLD from the positive input (IN+) to the negative input (IN-). This unbalances node ZERO at the comparator’s positive input. The capacitive digital- to-analog converter (DAC) adjusts during the remain- Figure 3a. MAX1295 Simplified Input Structure Figure 3b. MAX1297 Simplified Input Structure CH0 CH1 CH2 CH3 CH4 CH5 COM CSWITCH TRACK T/H SWITCH RIN 800 Ω CHOLD HOLD 12-BIT CAPACITIVE DAC VREF ZERO COMPARATOR – + 12pF SINGLE-ENDED MODE: IN+ = CH0–CH5, IN- = COM DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF CH0/CH1 AND CH2/CH3, AND CH4/CH5 AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL. INPUT MUX CH0 CH1 COM CSWITCH TRACK T/H SWITCH RIN 800 Ω CHOLD HOLD 12-BIT CAPACITIVE DAC VREF ZERO COMPARATOR – + 12pF SINGLE-ENDED MODE: IN+ = CH0–CH1, IN- = COM DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIR CH0/CH1 AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL. INPUT MUX |
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