265ksps, +3V, 6-/2-Channel, 12-Bit ADCs

with +2.5V Reference and Parallel Interface

10

______________________________________________________________________________________

der of the conversion cycle to restore node ZERO to 0V

within the limits of 12-bit resolution. This action is equiv-

turn forms a digital representation of the analog input

signal.

Analog Input Protection

Internal protection diodes, which clamp the analog

damage. However, for accurate conversions near full

less than (GND - 50mV).

If an analog input voltage exceeds the supplies by

more than 50mV, limit the forward-bias input current

to 4mA.

Track/Hold

The MAX1295/MAX1297 T/H stage enters its tracking

mode on WR’s rising edge. In external acquisition

mode, the part enters its hold mode on the next rising

edge of WR. In internal acquisition mode, the part

enters its hold mode on the fourth falling edge of clock

after writing the control byte. Note that in internal clock

mode this is approximately 1µs after writing the control

byte.

In single-ended operation, IN- is connected to COM

and the converter samples the positive “+” input. In

pseudo-differential operation, IN- connects to the nega-

pled. At the beginning of the next conversion, the

positive input connects back to IN+ and CHOLD

charges to the input signal.

The time required for the T/H stage to acquire an input

signal depends on how quickly its input capacitance is

charged. If the input signal’s source impedance is high,

the acquisition time lengthens and more time must be

allowed between conversions. The acquisition time,

the signal, and is also the minimum time required for

the signal to be acquired. Calculate this with the follow-

ing equation:

the input capacitance of the ADC. Source impedances

below 3k

Ω have no significant impact on the MAX1295/

MAX1297’s AC performance.

Higher source impedances can be used if a 0.01µF

capacitor is connected to the individual analog inputs.

A1

CH0

0

+

0

-

0

A0

0

1

CH2*

CH4*

+

-

0

1

0

+

CH3*

-

0

CH1

COM

1

CH5*

1

+

-

0

0

0

A2

+

-

1

0

1

-

+

1

Table 2. Channel Selection for Single-Ended Operation (SGL/DIF = 1)

Table 3. Channel Selection for Pseudo-Differential Operation (SGL/DIF = 0)

A1

CH0

0

+

0

-

0

A0

0

-

1

CH2*

CH4*

+

0

1

0

+

-

CH3*

0

CH1

1

CH5*

1

-

+

0

0

0

A2

+

-

1

0

1

-

+

1

*

Channels CH2–CH5 apply to MAX1295 only.

*

Channels CH2–CH5 apply to MAX1295 only.