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MAX1458 Datasheet(PDF) 6 Page - Maxim Integrated Products |
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MAX1458 Datasheet(HTML) 6 Page - Maxim Integrated Products |
6 / 20 page Table 1. Input-Referred Offset DAC Correction Values Programmable-Gain Amplifier The programmable-gain amplifier (PGA), which is used to set the coarse FSO, uses a switched-capacitor CMOS technology and contains eight selectable gain levels from 41 to 230, in increments of 27 (Table 2). The output of the PGA is fed to the output summing junc- tion. The three PGA gain bits A2, A1, and A0 are stored in the configuration register. Output Summing Junction The third stage in the analog signal path consists of a summing junction for the PGA output, offset correction, and the offset TC correction. Both the offset and the off- set TC correction voltages are gained by a factor of 2.3 before being fed into the summing junction, increasing the offset and offset TC correction range. The offset sign bit and offset TC sign bit are stored in the configu- ration register. The offset sign bit determines if the off- set correction voltage is added to (sign bit is high) or subtracted from (sign bit is low) the PGA output. Negative offset TC errors require a logic high for the offset TC sign bit. Alternately, positive offset TC errors dictate a logic low for the offset TC sign bit. The output of the summing junction is fed to the output buffer. Output Buffer OUT can drive 0.1µF of capacitance. If CS is brought low, OUT becomes high impedance (resulting in typical output impedance of 1M Ω). The output is current limit- ed and can be shorted to either VDD or VSS indefinitely. The maximum output voltage can be limited using the LIMIT pin. Output limiting can be performed for sensor diagnostic purposes. Connect LIMIT to VDD to disable the voltage-limiting feature. Bridge Drive Fine FSO correction is accomplished by varying the sensor excitation current with the 12-bit FSO DAC (Figure 3). Sensor bridge excitation is performed by a programmable current source capable of delivering up to 2mA. The reference current at ISRC is established by resistor RISRC and by the voltage at node ISRC (con- trolled by the FSO DAC). The reference current flowing through this pin is multiplied by a current mirror (AA ≅ 14) and then made available at BDRIVE for sensor exci- tation. Modulation of this current with respect to tem- perature can be used to correct FSOTC errors, while modulation with respect to the output voltage (VOUT) can be used to correct FSO linearity errors. Digital-to-Analog Converters The four 12-bit, sigma-delta DACs typically settle in less than 100ms. The four DACs have a corresponding memory register in EEPROM for storage of correction coefficients. Use the FSO DAC for fine FSO adjustments. The FSO DAC takes its reference from VDD and controls VISRC which, in conjunction with RISRC, sets the baseline sen- sor excitation current. The Offset DAC also takes its ref- erence from VDD and provides a 1.22mV resolution with 1%-Accurate, Digitally Trimmed Sensor Signal Conditioner 6 _______________________________________________________________________________________ +7 1 1 1 IRO DAC 1 OFFSET CORREC- TION % of VDD (%) +1.25 OFFSET CORREC- TION AT VDD = 5V (mV) +63 SIGN C1 C2 C0 VALUE +6 1 1 1 0 +1.08 +54 +5 1 1 0 1 +0.90 +45 +4 1 1 0 0 +0.72 +36 +3 1 0 1 1 +0.54 +27 +2 1 0 1 0 +0.36 +18 +1 1 0 0 1 +0.18 +9 +0 1 0 0 0 0 0 -0 0 0 0 0 -1 0 0 0 1 -0.18 -9 -2 0 0 1 0 -0.36 -18 -3 0 0 1 1 -0.54 -27 -4 0 1 0 0 -0.72 -36 -5 0 1 0 1 -0.90 -45 -6 0 1 1 0 -1.08 -54 -7 0 1 1 1 -1.25 -63 A1 0 0 0 A2 A0 PGA VALUE 0 PGA GAIN (V/V) 41 OUTPUT- REFERRED IRO DAC STEP SIZE (VDD = 5V) (V) 0.369 1 0 0 1 68 0.612 2 0 1 0 95 0.855 3 0 1 1 122 1.098 4 1 0 0 149 1.341 5 1 0 1 176 1.584 6 1 1 0 203 1.827 7 1 1 1 230 2.070 Table 2. PGA Gain Settings and IRO DAC Step Size 0 0 |
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