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MAX1462CCM Datasheet(PDF) 9 Page - Maxim Integrated Products |
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MAX1462CCM Datasheet(HTML) 9 Page - Maxim Integrated Products |
9 / 16 page hex). Fractional coefficient values range from -1.0 (8000 hex) to +0.99997 (7FFF hex). The register at address 0 is called the Configuration Register. It holds the CO, PGA gain, Op Amp Power- Down, temperature-sensor offset, repeat mode, and reserved bits, as shown in Table 6. The functionality of the CO, PGA gain, and temperature-sensor bits is described in the Analog Front End, Including PGA, CO- DAC, ADC, and Temperature Sensor section. The Op Amp Power-Down bit enables the uncommitted op amp when set. The repeat-mode bit is tested by the last instruction of the DSP microcode, and, if set, imme- diately initiates another conversion cycle. The Maxim reserved bits should not be altered. Writing to the Internal EEPROM The test system writes to the EEPROM with commands 4 hex (Block-Erase the entire EEPROM), 2 hex (Write 1 to a single EEPROM bit), and 0 hex (NOOP). The mini- mum VDD required for all EEPROM write operations is 4.75V. During normal operation (when the TEST pin is low) or when the test system issues instructions A hex or E hex (Start Conversion from EEPROM values), the DSP reads the Calibration Coefficients from the EEPROM. In the normal production flow, determine the calibration coefficients using direct register access. Then load the calibration coefficients into the EEPROM with tester instruction 2 hex. Instruction 4 hex block-erases the EEPROM and is necessary only for a rework or reclaim operation. For each part, the Maxim reserved bits in the Configuration Register should be read before instruc- tion 4 hex is issued, and restored afterwards. The MAX1462 is shipped with its internal EEPROM uninitial- ized, except for the reserved bits. Low-Voltage, Low-Power, 16-Bit Smart ADC _______________________________________________________________________________________ 9 MIN 16 CLK CYCLES COMMAND 1 REGISTER DATA FIELD EEPROM ADDRESS FIELD REG. ADD COMMAND 2 COMMAND 3 COMMAND n COMMAND 00 01 02 03 29 30 31 00 01 02 03 29 30 31 00 01 02 03 29 30 31 00 01 02 03 29 30 31 D0 D1 D2 D3 C3 NU NU D0 D1 D2 D3 C3 NU NU D0 D1 D2 D3 C3 NU NU D0 D1 D2 D3 C3 NU NU D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 E0 E1 E2 E3 E4 E5 E6 R0 R1 R2 C0 C1 C2 C3 NU NU MSB LSB LSB MSB LSB MSB LSB MSB NOTE: ALL TRANSITIONS MUST OCCUR WITHIN 100ns OF THE XIN CLOCK EDGE. XIN TEST RESET SDIO Figure 3. Test-System Command Timing Diagram Table 3. TSO Settings 0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 Maximum — — — — — — Minimum 5 1 0 1 6 1 1 0 7 1 1 1 TSO SETTING TEMPERATURE BRIDGE OFFSET TSO-2 TSO-1 TSO-0 |
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