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MAX149BEAP Datasheet(PDF) 5 Page - Maxim Integrated Products

Part # MAX149BEAP
Description  2.7V to 5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX149BEAP Datasheet(HTML) 5 Page - Maxim Integrated Products

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+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
_______________________________________________________________________________________
5
Figure 1
__________________________________________Typical Operating Characteristics
(VDD = 3.0V, VREF = 2.500V, fSCLK = 2.0MHz, CLOAD = 20pF, TA = +25°C, unless otherwise noted.)
0
256
512
768
1024
INTEGRAL NONLINEARITY
vs. CODE
0.10
0.05
-0.10
-0.05
0
CODE
0.125
0
2.25
2.75
4.25
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
0.100
0.075
0.050
0.025
SUPPLY VOLTAGE (V)
3.75
5.25
3.25
4.75
MAX149
MAX148
0
0.025
0.050
0.075
0.100
0.125
-60
-20
20
60
100
140
INTEGRAL NONLINEARITY
vs. TEMPERATURE
TEMPERATURE (°C)
MAX148
MAX149
VDD = 2.7V
TIMING CHARACTERISTICS
(VDD = +2.7V to +5.25V, TA = TMIN to TMAX, unless otherwise noted.)
Note 1: Tested at VDD = 2.7V; COM = 0V; unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: MAX149—internal reference, offset nulled; MAX148—external reference (VREF = +2.500V), offset nulled.
Note 4: Ground “on” channel; sine wave applied to all “off” channels.
Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from AGND to VDD.
Note 7: Sample tested to 0.1% AQL.
Note 8: External load should not change during conversion for specified accuracy.
Note 9: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 10: Guaranteed by design. Not subject to production testing.
Note 11: The MAX148 typically draws 400µA less than the values shown.
Note 12: Measured as
|VFS(2.7V) - VFS(5.25V)|.
Internal clock mode only (Note 7)
External clock mode only, Figure 2
External clock mode only, Figure 1
DIN to SCLK Setup
Figure 1
Figure 2
Figure 1
MAX14_ _C/E
CONDITIONS
MAX14_ _M
ns
20
240
Figure 1
ns
tCSH
ns
240
tSTR
CS Rise to SSTRB Output Disable
ns
240
tSDV
CS Fall to SSTRB Output Enable
240
tSSTRB
SCLK Fall to SSTRB
ns
200
tCL
SCLK Pulse Width Low
ns
200
SCLK Pulse Width High
ns
0
CS to SCLK Rise Hold
ns
100
tCSS
CS to SCLK Rise Setup
ns
240
tTR
CS Rise to Output Disable
ns
240
tDV
CS Fall to Output Enable
tCH
20
200
tDO
SCLK Fall to Output Data Valid
ns
0
tDH
DIN to SCLK Hold
ns
µs
1.5
tACQ
Acquisition Time
0
tSCK
SSTRB Rise to SCLK Rise
ns
100
tDS
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER


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