+2.7V, Low-Power, 8-Channel,

Serial 12-Bit ADCs

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5

Figure 1

__________________________________________Typical Operating Characteristics

0.5

0

1024

2048

3072

4096

INTEGRAL NONLINEARITY

vs. CODE

0.3

-0.3

-0.5

-0.1

0.1

0.4

0.2

-0.4

-0.2

0

CODE

0.50

0

2.25

2.75

4.25

INTEGRAL NONLINEARITY

vs. SUPPLY VOLTAGE

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

3.75

5.25

3.25

4.75

MAX146

MAX147

0

0.10

0.20

0.30

0.40

0.50

0.05

0.15

0.25

0.35

0.45

-60

-20

20

60

100

140

INTEGRAL NONLINEARITY

vs. TEMPERATURE

TEMPERATURE (°C)

MAX147

MAX146

TIMING CHARACTERISTICS

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has

been calibrated.

Note 3: MAX146—internal reference, offset nulled; MAX147—external reference (VREF = +2.500V), offset nulled.

Note 4: Ground “on” channel; sine wave applied to all “off” channels.

Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.

Note 7: External load should not change during conversion for specified accuracy.

Note 8: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.

Note 9: Guaranteed by design. Not subject to production testing.

Note 10: Measured as

Internal clock mode only (Note 9)

External clock mode only, Figure 2

External clock mode only, Figure 1

DIN to SCLK Setup

Figure 1

Figure 2

Figure 1

MAX14_ _C/E

CONDITIONS

MAX14_ _M

ns

20

240

Figure 1

ns

ns

240

CS Rise to SSTRB Output Disable

ns

240

CS Fall to SSTRB Output Enable

240

SCLK Fall to SSTRB

ns

200

SCLK Pulse Width Low

ns

200

SCLK Pulse Width High

ns

0

CS to SCLK Rise Hold

ns

100

CS to SCLK Rise Setup

ns

240

CS Rise to Output Disable

ns

240

CS Fall to Output Enable

20

200

SCLK Fall to Output Data Valid

ns

0

DIN to SCLK Hold

ns

µs

1.5

Acquisition Time

0

SSTRB Rise to SCLK Rise

ns

100

UNITS

MIN

TYP

MAX

SYMBOL

PARAMETER