AUIRS2332J

6

Recommended Operating Conditions

The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the

tested with all supplies biased at 15V differential.

Note 2: Operational for transient negative VS of VSS - 50 V with a 50 ns pulse width. Guaranteed by design. Refer

to the Application Information section of this datasheet for more details.

Note 3: CAO input pin is internally clamped with a 5.2 V zener diode.

Dynamic Electrical Characteristics

Unless otherwise noted, these specifications apply for an operating junction temperature range of -40°C

≤

Tj

Symbol

Definition

Min Typ Max Units

Test Conditions

Turn-on propagation delay

400

540

700

ns

Turn-off propagation delay

400

540

700

Turn-on rise time

—

80

145

Turn-off fall time

—

40

55

ITRIP to Output Shutdown Propagation

delay

400

625

920

ITRIP Blanking Time

—

400

—

ITRIP to FAULT Indication Delay

350

550

870

Input Filter Time (All Six Inputs)

—

325

—

LIN1,2,3 to FAULT Clear Time

5300 8500 13700

DT

Deadtime:

500

850

1100

external deadtime

MDT

Deadtime matching:

—

—

145

MT

—

—

50

external deadtime larger than DT

PM

Pulse width distortion

—

—

75

PM input 10 µs

SR+

Operational Amplifier Slew Rate (+)

5

10

—

V/µs

1 V input step

SR-

Operational Amplifier Slew Rate (-)

2.4

3.2

—

1 V input step

Symbol

Definition

Min.

Max.

Units

High Side Floating Supply Voltage

V

Static High side floating offset voltage

600

Transient High side floating offset voltage

-50 (Note2)

600

High Side Floating Output Voltage

Low Side and Logic Fixed Supply Voltage

10

20

Logic Ground

-5

5

Low Side Output Voltage

0

Logic Input Voltage (HIN1,2,3, LIN1,2,3 & ITRIP)

FAULT Output Voltage

Operational Amplifier Output Voltage

Operational Amplifier Inverting Input Voltage

Ambient temperature

-40

125

°C