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MAX1858AEEG Datasheet(PDF) 3 Page - Maxim Integrated Products |
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MAX1858AEEG Datasheet(HTML) 3 Page - Maxim Integrated Products |
3 / 22 page Dual 180° Out-of-Phase Buck Controllers with Sequencing/Prebias Startup and POR _______________________________________________________________________________________ 3 ELECTRICAL CHARACTERISTICS (continued) (V+ = 12V, EN = ILIM_ = VL, SYNC = GND, IVL = 0mA, PGND = GND, CREF = 0.22µF, CVL = 4.7µF (ceramic), ROSC = 60k Ω, compensation components for COMP_ are from Figure 1, TA = -40°C to +85°C (Note 1), unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS SYNC Range Switching frequency must be set to half of the SYNC frequency 200 1200 kHz High 100 SYNC Input Pulse Width (Note 4) Low 100 ns SYNC Rise/Fall Time (Note 4) 100 ns ERROR AMPLIFIER FB_ Input Bias Current 250 nA 0°C to +85°C 0.985 1.00 1.015 FB_ Input Voltage Set Point -40°C to +85°C 0.98 1.00 1.02 V 0°C to +85°C 1.25 1.8 2.70 FB_ to COMP_ Transconductance -40°C to +85°C 1.2 1.8 2.9 mS DRIVERS DL_, DH_ Break-Before-Make Time CLOAD = 5nF 30 ns Low 1.5 2.5 DH_ On-Resistance High 3 5 Ω Low 0.6 1.5 DL_ On-Resistance High 3 5 Ω LOGIC INPUTS (EN, SYNC) Input Low Level Typical 15% hysteresis, VL = 4.5V 0.8 V Input High Level VL = 5.5V 2.4 V Input High/Low Bias Current VEN = 0 or 5.5V -1 +0.1 +1 µA LOGIC OUTPUTS (CKO) Output Low Level VL = 5V, sinking 5mA 0.4 V Output High Level VL = 5V, sourcing 5mA 4.0 V COMP_ Pulldown Resistance During Shutdown and Current Limit 17 Ω RST OUTPUT (MAX1858A/MAX1876A ONLY) Output-Voltage Trip Level Both FBs must be over this to allow the reset timer to start; there is no hysteresis 0.87 0.9 0.93 V VL = 5V, sinking 3.2mA 0.4 Output Low Level VL = 1V, sinking 0.4mA 0.3 V Output Leakage V+ = VL = 5V, V RST = 5.5V, VFB = 1V 1 µA Reset Timeout Period VFB_ = 1V 140 315 560 ms FB_ to Reset Delay FB_ overdrive from 1V to 0.85V 4 µs Note 1: Specifications to -40°C are guaranteed by design and not production tested. Note 2: Operating supply range is guaranteed by VL line regulation test. Connect V+ to VL for 5V operation. Note 3: When VL falls and UVLO is tripped, the device is latched and VL must be discharged below 2.5V before normal operation can resume. Note 4: Guaranteed by design and not production tested. |
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