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74ALVC125 Datasheet(PDF) 2 Page - NXP Semiconductors |
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74ALVC125 Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 13 page 74ALVC125_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 10 January 2008 2 of 13 NXP Semiconductors 74ALVC125 Quad buffer/line driver; 3-state 4. Functional diagram 5. Pinning information 5.1 Pinning Fig 1. Logic symbol Fig 2. IEC logic symbol mna228 1A 1Y 2 1 3 1OE 2A 2Y 5 4 6 2OE 3A 3Y 9 10 8 3OE 4A 4Y 12 13 11 4OE mna229 1 EN1 1 3 2 4 6 5 10 8 9 13 11 12 Fig 3. Logic diagram (one buffer) mna227 nOE nA nY (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration SO14 and TSSOP14 Fig 5. Pin configuration DHVQFN14 74ALVC125 1OE VCC 1A 4OE 1Y 4A 2OE 4Y 2A 3OE 2Y 3A GND 3Y 001aah089 1 2 3 4 5 6 7 8 10 9 12 11 14 13 001aah090 74ALVC125 Transparent top view GND(1) 2Y 3A 2A 3OE 2OE 4Y 1Y 4A 1A 4OE 6 9 5 10 4 11 3 12 2 13 terminal 1 index area |
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