Track/Hold

In track mode, the analog signal is acquired and stored

in the internal hold capacitor. In hold mode, the T/H

switch opens and maintains a constant input to the

ADC’s SAR section.

During acquisition, the analog input AIN charges

interval. At this instant, the T/H switches the input side

resents a sample of the input, unbalancing the node

ZERO at the comparator’s input.

In hold mode, the capacitive DAC adjusts during the

remainder of the conversion cycle to restore node

ZERO to 0V within the limits of a 12-bit resolution. This

action is equivalent to transferring a charge from

turn forms a digital representation of the analog input

signal again.

The time required for the T/H to acquire an input signal

is a function of how quickly its input capacitance is

charged. If the input signal’s source impedance is

high, the acquisition time lengthens and more time

must be allowed between conversions. Acquisition time

is calculated by:

impedances below 5k

Ω do not significantly affect the

AC performance of the ADC.

+5V, Low-Power, 12-Bit Serial ADCs

_______________________________________________________________________________________

9

AIN

TRACK INPUT

HOLD

CPACKAGE

GND

TRACK

HOLD

5k

CHOLD

16pF

-+

CSWITCH

COMPARATOR

ZERO

REF

12-BIT CAPACITIVE DAC

AT THE SAMPLING INSTANT,

THE INPUT SWITCHES FROM

AIN TO GND.

ON

OFF

SHUTDOWN

INPUT

ANALOG INPUT

0V TO +5V

+5V

1

2

3

4

VDD

AIN

SHDN

REF

8

7

6

5

SCLK

CS

DOUT

GND

SERIAL

INTERFACE

0.1

µF

4.7

µF

0.1

µF

REFERENCE

INPUT

MAX189

ON

OFF

SHUTDOWN

INPUT

ANALOG INPUT

0V TO +5V

+5V

1

2

3

4

VDD

AIN

SHDN

REF

8

7

6

5

SCLK

CS

DOUT

GND

SERIAL

INTERFACE

4.7

µF

4.7

µF

0.1

µF

MAX187

Figure 3a. MAX187 Operational Diagram

Figure 3b. MAX189 Operational Diagram

Figure 4. Equivalent Input Circuit