2) Use a general-purpose I/O line on the CPU to pull

CS on the MAX186/MAX188 low.

3) Transmit TB1 and simultaneously receive a byte

and call it RB1. Ignore RB1.

4) Transmit a byte of all zeros ($00 HEX) and simulta-

neously receive byte RB2.

5) Transmit a byte of all zeros ($00 HEX) and simulta-

neously receive byte RB3.

6) Pull

CS on the MAX186/MAX188 high.

Figure 6 shows the timing for this sequence. Bytes RB2

and RB3 will contain the result of the conversion

padded with one leading zero and three trailing zeros.

The total conversion time is a function of the serial

clock frequency and the amount of dead time between

8-bit transfers. Make sure that the total conversion time

does not exceed 120µs, to avoid excessive T/H droop.

Digital Output

In unipolar input mode, the output is straight binary

(see Figure 15). For bipolar inputs, the output is

twos-complement (see Figure 16). Data is clocked out

at the falling edge of SCLK in MSB-first format.

Low-Power, 8-Channel,

Serial 12-Bit ADCs

______________________________________________________________________________________

11

SEL2

SEL1

SEL0

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

AGND

00

0

+

–

10

0

+

–

00

1

+

–

10

1

+

–

01

0

+

–

11

0

+

–

01

1

+

–

11

1

+

–

Table 3. Channel Selection in Single-Ended Mode (SGL/

DIFF = 1)

SEL2

SEL1

SEL0

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

00

0

+

–

00

1

+

–

01

0

+

–

01

1

+–

10

0

–

+

10

1

–

+

11

0

–

+

11

1

–+

Table 4. Channel Selection in Differential Mode (SGL/

DIFF = 0)