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MAX2102 Datasheet(PDF) 10 Page - Maxim Integrated Products |
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MAX2102 Datasheet(HTML) 10 Page - Maxim Integrated Products |
10 / 16 page Direct-Conversion Tuner ICs for Digital DBS Applications 10 ______________________________________________________________________________________ VCC 28 27 26 25 24 23 22 21 20 56 Ω 33 Ω 19 18 17 16 15 0.22 µF 0.22 µF 22pF 22pF 10pF 1000pF 22 Ω 10pF 2 1 3 4 5 6 7 8 9 10 11 12 13 14 IOUT GND RFIN RFIN GND GND VCC VCC VCC VCC AGC CONTROL VCC 100 Ω LOAD AGC GND GND QOUT VCC VCC VCC VCC PRESCALER OUTPUT LO INPUT (50 Ω SOURCE) MODULUS CONTROL VCC MOD PSOUT LO LO GND VCC PSGND VCC GND IDC IDC QDC QDC 10pF 1000pF VCC 22pF 22pF 22pF 22pF 51 Ω 0.1 µF 0.1 µF 10pF 47 µF 0.1 µF 47 µF RF INPUT (50 Ω SOURCE) MAX2102 MAX2105 2k Ω 100 Ω LOAD 0.1 µF Figure 1. Typical Operating Circuit Detailed Description The MAX2102/MAX2105 down-convert signals in the range 950MHz to 2150MHz directly to baseband I/Q signals. They are targeted for digital DBS tuner applica- tions where a direct downconversion provides a cost savings over prior-art, multiple-conversion approaches. However, the MAX2102/MAX2105 are applicable to any system requiring a broadband I/Q downconversion. Internally, the MAX2102 and MAX2105 consist of a broadband front-end variable gain stage, a quadrature downconverter, an oscillator buffer, high-linearity I and Q baseband amplifiers, and offset correction amplifiers. The MAX2102 features a front-end AGC dynamic range of over 50dB, while the MAX2105 provides a front-end AGC dynamic range of over 41dB. Specifically, the AGC control can be adjusted so that a sine wave at RFIN ranging in power from -69dBm to -19dBm (MAX2102) or -60dBm to -19dBm (MAX2105) will pro- duce a sine wave at IOUT and QOUT at 500mVp-p lev- els. The noise figure is lowest when the AGC is at its maximum gain setting (see Typical Operating Characteristics). The VSWR at RFIN is unaffected by the AGC setting. The local-oscillator (LO) buffer accepts an external LO signal at LO, LO, and internally limits the signal to pro- vide a consistent on-chip LO level. The LO input drive level should be maintained within the specified limits (see Applications Information section). |
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