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74AUP2G34 Datasheet(PDF) 3 Page - NXP Semiconductors |
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74AUP2G34 Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 19 page 74AUP2G34 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 10 January 2013 3 of 19 NXP Semiconductors 74AUP2G34 Low-power dual buffer 6. Pinning information 6.1 Pinning 6.2 Pin description 7. Functional description [1] H = HIGH voltage level; L = LOW voltage level. Fig 4. Pin configuration SOT363 Fig 5. Pin configuration SOT886 Fig 6. Pin configuration SOT891, SOT1115 and SOT1202 74AUP2G34 1A 1Y GND 2A 2Y 001aad702 1 2 3 6 VCC 5 4 74AUP2G34 GND 001aad703 1A 2A VCC 1Y 2Y Transparent top view 2 3 1 5 4 6 74AUP2G34 GND 001aad667 1A 2A VCC 1Y 2Y Transparent top view 2 3 1 5 4 6 Table 3. Pin description Symbol Pin Description 1A 1 data input GND 2 ground (0 V) 2A 3 data input 2Y 4 data output VCC 5 supply voltage 1Y 6 data output Table 4. Function table[1] Input Output nA nY LL HH |
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Similar Description - 74AUP2G34_15 |
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