IR1161LPBF

10

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June 1, 2015

Application Information and Additional Details

State Diagram

POWER ON

Gate Inactive

UVLO MODE

VCC < VCC on

ICC < ICC start

Gate Inactive

NORMAL

Gate Active

Gate PW

≥ MOT

Cycle by Cycle MOT Check Enabled

VCC > VCCon,

VCC < VCCuvlo

MOT PROTECTION

MODE

Gate Output Disabled

UVLO Mode

During the time the IC remains in the UVLO state, the gate drive circuit is inactive and only a very small quiescent

Normal Mode and Synchronized Enable Function

The IC enters into normal operating mode once the UVLO voltage has been exceeded. When the IC enters the

Normal Mode, the GATE output remains disabled (stays low) for a start-up delay time in the range of 100us, then

can never be enabled in the middle of a switching cycle. The first gate pulse after activation is blocked and the

cycle by cycle MOT protection circuit is enabled. This logic avoids reverse currents through the SR MOSFET from

occurring during startup. The gate will continuously drive the SR MOSFET after completing this startup sequence.

MOT Protection Mode

If the secondary current conduction time is shorter than the MOT (Minimum On Time), the following driver output

pulse is disabled. This function can avoid reverse current from occurring when the system is switching at very low

duty-cycles under very light or zero load conditions. System standby power consumption is reduced by disabling

the GATE output. The cycle by cycle MOT check circuit is always activated under Normal Mode and MOT

Protection Mode so that the IC will automatically resume normal operation only once the load increases to a level

where the secondary current conduction time exceeds MOT.