2.5GHz, +20dBm Power Amplifier IC

in UCSP Package

8

____________________________________________________________________________________________________

SHDN

SHDN is located in the center of the bump layout of the

MAX2240. Therefore, the SHDN line requires the use of

either a via to a buried line or a trace that fits inside a

10-mil gap between solder pads to bring out a connec-

tion from SHDN.

D0, D1 Pins

Digital power control inputs D0 and D1 have CMOS-

logic level inputs. As in any PC board circuit, the length

of the logic signal traces determines the susceptibility

to high-frequency noise that can interfere with normal

switching. Therefore, in some cases, it can be neces-

sary to provide some local lowpass filtering of the logic

traces to suppress HF noise coupling to these inputs.

Output Match Layout

It is possible to lay out the output matching network

transmission traces in a more compact manner if PC

board area is limited. Series lines T1 and T2 can be

constructed as folded lines, though it can be necessary

to chamfer the corners for wide lines.

Prototype Chip Installation

Alignment keys on the PC board around the area where

the chip is located are helpful in the prototype assembly

process. The MAX2240 EV kit PC board has L-shaped

alignment keys at the diagonal corners of the chip. It is

better to align the chip on the board before any other

components are placed, and then place the board on a

hotplate or hot surface until the solder starts melting.

Remove the board from the hotplate without disturbing

the position of the chip, and let it cool down to room tem-

perature before processing the board further.

UCSP Reliability

The UCSP represents a unique packaging form factor that

may not perform equally to a packaged product through

traditional mechanical reliability tests. CSP reliability is

integrally linked to the user’s assembly methods, circuit

board material, and usage environment. The user should

closely review these areas when considering use of a CSP

package. Performance through Operating Life Test and

Moisture Resistance remains uncompromised as it is pri-

marily determined by the wafer-fabrication process.

Mechanical stress performance is a greater consideration

for a CSP package. CSPs are attached through direct sol-

der contact to the user’s PC board, foregoing the inherent

stress relief of a packaged product lead frame. Solder

joint contact integrity must be considered. Table 2 shows

the testing done to characterize the CSP reliability perfor-

mance. In conclusion, the UCSP is capable of performing

reliably through environmental stresses as indicated by

the results in the table. Additional usage data and recom-

mendations are detailed in the UCSP application note,

which can be found on Maxim’s web- site at www.maxim-

ic.com.

Users should also be aware that, as with any interconnect

system, there are electromigration-based current limits

that, in this case, apply to the maximum allowable current

in the bumps. Reliability is a function of this current, the

duty cycle, lifetime, and bump temperature. See the

Absolute Maximum Ratings section for any specific limita-

tions, listed under Continuous Operating Lifetime.

TEST

CONDITIONS

DURATION

NO. OF FAILURES PER

SAMPLE SIZE

Temperature Cycle

-35

°C to +85°C,

-40

°C to +100°C

150 cycles,

900 cycles

0/10,

0/200

Operating Life

°C

240hr

0/10

Moisture Resistance

+20

°C to +60°C, 90% RH

240hr

0/10

Low-Temperature Storage

-20

°C

240hr

0/10

Low-Temperature

Operational

-10

°C

24hr

0/10

Solderability

8hr steam age

—

0/15

ESD

±2000V, Human Body Model

—

0/5

High-Temperature Operating

Life

°C

168hr

0/45

Table 2. Reliability Test Data