Receive IF Filter

The interstage filter, located between the MIXOUT pin

and the LIMIN pin, is typically a three-terminal, 330

Ω,

10.7MHz bandpass filter. This filter prevents the limiter

from acting on any undesired signals that are present

at the mixer’s output, such as LO feedthrough, out-of-

band channel leakage, and spurious mixer products.

The filter connections are also set up to feed DC bias

from VREF into LIMIN and MIXOUT through two 330

Ω

filter-termination resistors. (See the

Typical Operating

Circuit for more information).

Transmit Output Matching

The transmit outputs, TXOUT and TXOUT, are open-

collector outputs and therefore present a high

impedance.

For differential drive, TXOUT and TXOUT are connected

load. A terminating resistor between TXOUT and

TXOUT sets the output impedance. This resistor pro-

vides a stable means of matching to the load.

TXOUT and TXOUT are voltage-swing limited, and

therefore cannot drive the specified maximum power

across more than 150

Ω load impedance. This load

impedance typically consists of a shunt-terminating

resistor in parallel with a filter load impedance. To drive

higher output load impedances, the gain must be

reduced (via the GC pin) to avoid saturating the TX out-

put stage.

For single-ended applications, connect the unused TX

400MHz ISM Applications

The MAX2510 can be used as a front-end IC in appli-

cations where the RF carrier frequency is in the

400MHz ISM band. In this case, Maxim recommends

preceding the MAX2510 receiver section with a low-

noise amplifier (LNA) that can operate over the same

supply voltage range. The MAX2630–MAX2633 family

of amplifiers meets this requirement. In many applica-

tions, the MAX2510’s transmit output power is sufficient

to eliminate the need for an external power amplifier.

______________________Layout Issues

A well-designed PC board is an essential part of an RF

circuit. Use the MAX2510 evaluation kit and the recom-

mendations below as guides to generate your own

layout.

Power-Supply Layout

A star topology, which has a heavily decoupled central

ing coupling between different sections of the chip. The

circuit. At the end of each of these traces is a bypass

capacitor that presents low impedance at the RF fre-

quency of interest. This method provides local decou-

leaking out of a supply pin sees a relatively high imped-

other supply pin, minimizing Vcc supply-pin coupling.

A single ground plane suffices. Where possible, multi-

ple parallel vias aid in reducing inductance to the

ground plane.

Place the VREF decoupling capacitor (0.1µF typical) as

close to the MAX2510 as possible for best interstage fil-

ter performance. For best results, use a high-quality,

low-ESR capacitor.

Matching/biasing networks around the receive and

transmit pins should be symmetric and as close to the

chip as possible. A cutout in the ground plane under

the matching network components can be used to

reduce parasitic capacitance.

Tx ground), which should be directly connected the

ground plane. Similarly, decouple pin 8 directly to pin 7.

Refer to the

Pin Description table for more information.

Low-Voltage IF Transceiver with

Limiter/RSSI and Quadrature Modulator

______________________________________________________________________________________

11

64 - j109

94 - j143

149 - j184

SERIES IMPEDANCE

(

Ω)

275 - j203

400

300

200

FREQUENCY

(MHz)

100

53 - j87

500