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AFBR-810BEHZ Datasheet(PDF) 4 Page - AVAGO TECHNOLOGIES LIMITED |
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AFBR-810BEHZ Datasheet(HTML) 4 Page - AVAGO TECHNOLOGIES LIMITED |
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4 / 48 page  4 Figure 3. Application Reference Diagram ASIC/SerDes FO Tx (1 of 12 Lanes) Host Board Electrical Interface - Compliance Points - FO Rx Electrical Interface FO Rx (1 of 12 Lanes) FO Tx Electrical Interface SDD22 SCC22 SCC11 SDD11 SCD11 SDC22 CAC CAC 50 Ω 50 Ω 50 Ω 50 Ω High Speed Signal Interface Figure 3 shows the interface between an ASIC/SerDes and the fiber Optic modules. For simplicity, only one channel is shown. As shown in the Figure 3, the compliance points are on the host board side of the electrical connectors.Sets of s-parameters are defined for the transmitter and receiver interfaces. The transmitter and receiver are designed, when operating within Recommended Operating Con- ditions, to provide a robust eye-opening at the receiver outputs. See the Recommended Operating Conditions and the Receiver Electrical Characteristics for details. Unused inputs and outputs should be terminated with 100 Ω differential loads. The transmitter inputs support a wide common mode range and DC blocking capacitors may not be needed – none are shown in Figure 3. Depending on the common mode range tolerance of the ASIC/SerDes inputs, DC blocking capacitors may be required in series with the receiver. Differential impedances are nominally 100 Ω. The common mode output impedance for the receiver is nominally 25 Ω while the nominal common mode input impedance of the transmitter is 25 Ω. Figure 4. Input Equalization Frequency No Equalization Maximum Equalization Transmitter Input Equalization Transmitter inputs can be programmed for one of several levels of equalization. See Figure 4. Different levels of compensation can be selected to equalize skin-effect losses across the host circuit board. See Tx Memory Map 01h Upper Page section addresses 228 - 233 for program- ming details. |
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