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MAX2740ECM Datasheet(PDF) 6 Page - Maxim Integrated Products |
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MAX2740ECM Datasheet(HTML) 6 Page - Maxim Integrated Products |
6 / 8 page Applications Information Figure 1 shows a typical application diagram in which the MAX2740 should be used. The RF front end con- sists of the antenna interface, MAX2740, two control loops (one for the AGC, the other for the synthesizer), and appropriate external components, including filters for image rejection and channel selectivity, operational amplifiers for the control loops, and resonator and tun- ing network for the VCO. Only the antenna input, an external 20MHz frequency reference, and an AGC input from the accompanying DSP are required. A differential output is provided from the MAX2740, which can be applied either to the exter- nal analog-to-digital conversion circuitry or directly to the companion DSP. Low-Noise Amplifier This subcircuit requires input and output matching. The input match is typically a series capacitor, and the out- put is typically a shunt inductor to VCC and a series capacitor. RF Mixer The RF input is matched externally. The match consists of a series inductor and shunt capacitor. The source impedance for this circuit is the single-ended, 50 Ω RF SAW used as an image reject filter. A second RF input is brought out to a separate pin for AC grounding. This ensures low ground impedance over a wide band and minimizes amplification of any noise at the IF frequency generated within the mixer structure. The IF output is delivered through low-output-imped- ance emitter followers and is suitable for directly driving a 135MHz IF SAW with a typical impedance of 400 Ω. The deliberate mismatch keeps the group delay distor- tion of the SAW within an acceptable level. IF Mixer The IF downconverter receives the differential 1st IF of 135.42MHz from the SAW and delivers a differential 2nd IF signal at 15.42MHz. The circuit has been opti- mized to deliver a high level of conversion gain with adequate IIP3 and noise figure. The circuit is terminat- ed on the input with a differential 100 Ω to establish the correct embedding impedance for the IF SAW. The emitter follower outputs drive directly into a high-imped- ance, differential, three-pole lowpass discrete lumped element filter. Variable-Gain Amplifier This circuit compensates for receiver gain variation and unknown antenna cable losses. Under these condi- tions, the receiver will exhibit minimum implementation loss. The circuit has a useful gain control range of greater than 50dB, with a maximum gain level of 16dB. Fixed-Gain Amplifier This circuit has been designed to deliver 40dB of differ- ential gain at the 2nd IF frequency of 15.42MHz. The differential inputs are received from the VGA outputs through a balanced lowpass filter circuit. The circuit’s differential output is designed to drive a digitizer with a typical load impedance of 4k Ω differential. Voltage-Controlled Oscillator The core of the L-band VCO is based on a common- collector Colpitts topology. This circuit has been opti- mized for low thermal noise and high signal swing with- out asymmetrical clipping. The circuit is designed for use with a lumped inductor for low-cost applications. The self-resonance should be above 1440MHz so that parallel varactor tuning and the VCO internal capaci- tance produces resonance at 1440MHz. Synthesizer The digital prescaler accepts the output from the oscil- lator’s differential digital buffer and divides the frequen- cy from 1.44GHz to 120MHz for the 2nd LO, 20MHz for the phase-frequency detector, and 90MHz for the GLONASS reference output. Divider blocks are arranged to ensure that the 2nd LO drive has minimum duty cycle distortion. A simple output buffer is used to deliver the GLONASS reference signal to a typical external load impedance of 500 Ω. The phase-frequency detector is a classical dual flip- flop with ANDed feedback to a reset function. UP and DOWN outputs are provided through emitter follower buffers. These outputs deliver pulse-width-modulated signals that in phase-acquisition mode give a phase detector range of ±2 π. With the PLL not in lock, either the UP or DOWN output will be active and drive the VCO frequency toward the reference frequency. The phase detector outputs feed directly into an active, lead-lag differential loop filter. Integrated GPS Receiver and Synthesizer 6 _______________________________________________________________________________________ |
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