+5V, Fail-Safe, 20Mbps, Profibus RS-485/

RS-422 Transceivers

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Detailed Description

The MAX3460–MAX3464 high-speed transceivers for

RS-485/RS-422 communication contain one driver and

one receiver. These devices feature true fail-safe cir-

cuitry, which guarantees a logic-high receiver output

when the receiver inputs are open or shorted, or when

they are connected to a terminated transmission line

with all drivers disabled (see the True Fail-Safe sec-

tion). The MAX3460–MAX3464’s driver slew rates allow

transmit speeds up to 20Mbps.

The MAX3463 and MAX3464 are half-duplex trans-

ceivers, while the MAX3460, MAX3461, and MAX3462

are full-duplex transceivers. All of these parts operate

from a single +5V supply. Drivers are output short-cir-

cuit current limited. Thermal shutdown circuitry protects

drivers against excessive power dissipation. When acti-

vated, the thermal shutdown circuitry places the driver

outputs into a high-impedance state. The MAX3460

and MAX3463 devices have a hot-swap input structure

that prevents disturbances on the differential signal

lines when a circuit board is plugged into a “hot” back-

plane (see Hot Swap section). All devices have output

levels that are compatible with Profibus standards.

True Fail-Safe

The MAX3460–MAX3464 guarantee a logic-high receiv-

er output when the receiver inputs are shorted or open,

or when they are connected to a terminated transmis-

sion line with all drivers disabled. This is done by set-

ting the receiver threshold between -50mV and

-200mV. If the differential receiver input voltage (A - B)

is greater than or equal to -50mV, RO is logic high. If A

- B is less than or equal to -200mV, RO is logic low. In

the case of a terminated bus with all transmitters dis-

abled, the receiver’s differential input voltage is pulled

to 0V by the termination. With the receiver thresholds of

the MAX3460–MAX3464, this results in a logic high with

a 50mV minimum noise margin. Unlike previous true

fail-safe devices, the -50mV to -200mV threshold com-

plies with the ±200mV EIA/TIA-485 standard.

Hot-Swap Capability

Hot-Swap Inputs

When circuit boards are inserted into a “hot” or pow-

ered backplane, disturbances to the enable and differ-

ential receiver inputs can lead to data errors. Upon

initial circuit board insertion, the processor undergoes

its power-up sequence. During this period, the output

drivers are high impedance and are unable to drive the

DE input of the MAX3460/MAX3463 to a defined logic

level. Leakage currents up to 10µA from the high-

impedance output could cause DE to drift to an incor-

rect logic state. Additionally, parasitic circuit board

DE. These factors could improperly enable the driver.

low for around 15µs. After the initial power-up

sequence, the pulldown circuit becomes transparent,

resetting the hot-swap tolerable input.

Hot-Swap Input Circuitry

The MAX3460/MAX3463 enable inputs feature hot-swap

capability. At the input there are two NMOS devices, M1

15µs timer turns on M2 and sets the SR latch, which

also turns on M1. Transistors M2, a 2mA current sink,

and M1, a 100µA current sink, pull DE to GND through a

5.6k

Ω resistor. M2 is designed to pull DE to the disabled

state against an external parasitic capacitance up to

100pF that can drive DE high. After 15µs, the timer

deactivates M2 while M1 remains on, holding DE low

against three-state leakages that can drive DE high. M1

remains on until an external source overcomes the

required input current. At this time, the SR latch resets

and M1 turns off. When M1 turns off, DE reverts to a

drops below 1V, the hot-swap input is reset.

For RE there is a complimentary circuit employing two

TIMER

TIMER

EN

DE

(HOT SWAP)

15

µs

100

µA

M1

M2

5.6k

Ω

2mA

Figure 4. Simplified Structure of the Driver Enable Pin (DE)