+3.3V, 622Mbps, SDH/SONET 4:1 Serializer

with Clock Synthesis and LVDS Inputs

6

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Low-Voltage Differential-Signal (LVDS)

Inputs and Outputs

The MAX3693 features LVDS inputs and outputs for

interfacing with high-speed digital circuitry. The LVDS

standard is based on the IEEE 1596.3 LVDS specifi-

cation. This technology uses 250mV to 400mV differ-

ential low-voltage swings to achieve fast transition

times, minimized power dissipation, and noise immu-

nity.

For proper operation, the parallel-clock LVDS outputs

(PCLKO+, PCLKO-) require 100

Ω differential DC termi-

nation between the inverting and noninverting outputs.

Do not terminate these outputs to ground.

The parallel data and parallel clock LVDS inputs (PD_+,

PD_-, PCLKI+, PCLKI-, RCLK+, RCLK-) are internally

terminated with 100

Ω differential input resistance, and

therefore do not require external termination.

PECL Outputs

The serial-data PECL outputs (SD+, SD-) require 50

Ω

Output Termination section).

SD

NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCLKO = (PCLKO+) - (PCLKO-).

*PD3 = D3; PD2 = D2; PD1 = D1; PD0 = D0.

D0

D1

D2

D3

PD_

VALID PARALLEL DATA*

PCLKI

PCLKO

Figure 2. Timing Diagram