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8T49N242 Datasheet(PDF) 9 Page - Integrated Circuit Systems |
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8T49N242 Datasheet(HTML) 9 Page - Integrated Circuit Systems |
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9 / 65 page  REVISION 2 08/07/15 9 FEMTOCLOCK®NG UNIVERSAL FREQUENCY TRANSLATOR 8T49N242 DATA SHEET Output Drivers The Q0 to Q3 clock outputs are provided with register-controlled output drivers. By selecting the output drive type in the appropriate register, any of these outputs can support LVCMOS, LVPECL, HCSL or LVDS logic levels. The operating voltage ranges of each output is determined by its independent output power pin (VCCO) and thus each can have different output voltage levels. Output voltage levels of 2.5V or 3.3V are supported for differential operation and LVCMOS operation. In addition, LVCMOS output operation supports 1.8V VCCO. Each output may be enabled or disabled by register bits and/or GPIO pins. LVCMOS Operation When a given output is configured to provide LVCMOS levels, then both the Q and nQ outputs will toggle at the selected output frequency. All the previously described configuration and control apply equally to both outputs. Frequency, voltage levels and enable / disable status apply to both the Q and nQ pins. When configured as LVCMOS, the Q & nQ outputs can be selected to be phase-aligned with each other or inverted relative to one another. Selection of phase-alignment may have negative effects on the phase noise performance of any part of the device due to increased simultaneous switching noise within the device. Power-Saving Modes To allow the device to consume the least power possible for a given application, the following functions can be disabled via register programming: • Any unused output, including all output divider logic, can be individually powered-off. • Any unused input, including the clock monitoring logic can be individually powered-off. • The digital PLL can be powered-off when running in synthesizer mode. • Clock gating on logic that is not being used. Status / Control Signals and Interrupts The status and control signals for the device, may be operated at 1.8V, 2.5V or 3.3V as determined by the voltage applied to the VCCCS pins. All signals will share the same voltage levels. Signals involved include: nWP, nINT, nRST, GPIO[3:0], S_A0, S_A1, SCLK and SDATA. The voltage used here is independent of the voltage chosen for the digital and analog core voltages and the output voltages selected for the clock outputs. General-Purpose I/Os & Interrupts The 8T49N242 provides four General Purpose Input / Output (GPIO) pins for miscellaneous status & control functions. Each GPIO may be configured as either an input or an output. Each GPIO may be directly controlled from register bits or be used as a predefined function as shown in Table 4. Note that the default state prior to configuration being loaded from internal OTP will be to set each GPIO to input direction to function as an Output Enable. Table 4. GPIO Configuration If used in the Fixed Function mode of operation, the GPIO bits will reflect the real-time status of their respective status bits as shown in Table 4. The LOL alarm will support two modes of operation: • De-asserts once PLL is locked, or • De-asserts after PLL is locked and all internal synchronization operations that may destabilize output clocks are completed. Interrupt Functionality Interrupt functionality includes an interrupt status flag for each of PLL Loss-of-Lock status (LOL), PLL in holdover status (HOLD) and Loss-of-Signal status for each input (LOS[1:0]). Those Status Flags are set whenever there is an alarm on their respective functions. The Status Flag will remain set until the alarm has been cleared and a ‘1’ has been written to the Status Flag’s register location or if a reset occurs. Each Status Flag will also have an Interrupt Enable bit that will determine if that Status Flag is allowed to cause the Device Interrupt Status to be affected (enabled) or not (disabled). All Interrupt Enable bits will be in the disabled state after reset. The Device Interrupt Status Flag and nINT output pin are asserted if any of the enabled interrupt Status Flags are set. GPIO Pin Configured as Input Configured as Output Fixed Function (default) General Purpose Fixed Function General Purpose 3 - GPI[3] LOL GPO[3] 2 CSEL GPI[2] LOS[0] GPO[2] 1 OSEL[1] GPI[1] LOS[1] GPO[1] 0 OSEL[0] GPI[0] HOLD GPO[0] |
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