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8T49N285 Datasheet(PDF) 8 Page - Integrated Circuit Systems |
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8T49N285 Datasheet(HTML) 8 Page - Integrated Circuit Systems |
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8 / 65 page  8T49N285 DATA SHEET FEMTOCLOCK® NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR 8 REVISION 3 06/29/15 Input to Output Clock Frequency The 8T49N285 is designed to accept any frequency within its input range and generate eight different output frequencies that are independent from the input frequencies. The internal architecture of the device ensures that most translations will result in the exact output frequency specified. Where exact frequency translation is not possible, the frequency translation error will be minimized. Please contact IDT for configuration software or other assistance in determining if a desired configuration will be supported exactly. Synthesizer Mode Operation The device may also act as a frequency synthesizer with the PLL generating its operating frequency from just the crystal input. By setting the SYN_MODE register bit and setting the STATE[1:0] field to Freerun, no input clock references are required to generate the desired output frequencies. Loop Filter and Bandwidth When operating in Synthesizer Mode as described above, the 8T49N285 has a fixed loop bandwidth of approximately 200kHz. When Operating in all other modes, the following information applies: The 8T49N285 uses no external components to support a range of loop bandwidths:1.40625Hz, 2.8125Hz, 5.625Hz, 11.25Hz, 22.5Hz, 45Hz, 90Hz, 180Hz or 360Hz. The device supports two different loop bandwidth settings: acquisition and locked. These loop bandwidths are selected from the list of options described above. If enabled, the acquisition bandwidth is used while lock is being acquired to allow the PLL to “fast-lock”. Once locked the PLL will use the locked bandwidth setting. If the acquisition bandwidth setting is not used, the PLL will use the locked bandwidth setting at all times. Output Dividers The 8T49N285 supports eight output dividers. Six of the output dividers will have IntN capability only (see Table 3) and the other two will support FracN division. Integer Output Divider Programming (Q0, Q1, Q[4:7] only) Each integer output divider block consists of two divider stages in a series to achieve the desired total output divider ratio. The first stage divider may be set to divide by 4, 5 or 6. The second stage of the divider may be bypassed (i.e. ÷1) or programmed to any even divider ratio from 2 to 131,070. The total divide ratios, settings and possible output frequencies are shown in Table 3. In addition, the first divider stage for the Q[4:7] outputs support a bypass (i.e. ÷1) operation for some clock sources. Fractional Output Divider Programming (Q2, Q3 only) For the FracN output dividers Q2, Q3, the output divide ratio is given by: Output Divide Ratio = (N.F)x2 N = Integer Part: 4, 5, ...(218-1) F = Fractional Part: [0, 1, 2, ...(228-1)]/(228) For integer operation of these output dividers, N = 3 is also supported. Table 3. Q[0:1], Q[4:7] Output Divide Ratios NOTE: Above frequency ranges for Q[4:7] apply when driven di- rectly from the PLL. Output Divider Frequency Sources Output dividers associated with the Q[0:3] outputs take their input frequency directly from the PLL. Output dividers associated with the Q[4:7] outputs can take their input frequencies from the PLL, Q2 or Q3 output dividers, CLK0 or CLK1 input reference frequency or the crystal frequency. Output Banks Outputs of the 8T49N285 are divided into three banks for purposes of output skew measurement: • Q0, nQ0, Q1, nQ1 • Q4, nQ4, Q5, nQ5 • Q6, nQ6, Q7, nQ7 Output Phase Control on Switchover When the 8T49N285 switches between input references or enters or leaves the holdover state, there are two options on how the output phase can be controlled in these events: phase-slope limiting or fully hitless switching (sometimes called phase build-out) may be selected. The SWMODE bit selects which behavior is to be followed. If fully hitless switching is selected, then the output phase will remain unchanged under any of these conditions. Note that fully hitless switching is not supported when external loopback is being used. Fully hitless switching should not be used unless all input references are in the same clock domain. Note that use of this mode may prevent an output frequency and phase from being able to trace its alignment back to a primary reference source. 1st-Stage Divide 2nd-Stage Divide Total Divide Minimum FOUT MHz Maximum FOUT MHz 4 1 4 750 1000 5 1 5 600 800 6 1 6 500 666.7 4 2 8 375 500 5 2 10 300 400 6 2 12 250 333.3 4 4 16 187.5 250 5 4 20 150 200 6 4 24 125 166.7 ... 4 131,070 524,280 0.0057 0.0076 5 131,070 655,350 0.0046 0.0061 6 131,070 786,420 0.0038 0.0051 |
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