+3.3V, 2.5Gbps, SDH/SONET, 4-Channel

Interconnect Mux/Demux ICs with Clock Generator

10

______________________________________________________________________________________

clock cycle between each channel. In this test mode, ser-

ial data is internally looped back to the demux. All frame

detect logic is exercised using this mode. The CML

inputs (SDI± and SCLKI±) and LVDS inputs (PDI_±) are

ignored in this mode. After the BIST mode is enabled, the

loss-of-frame flag LOF goes high, indicating that the self-

test has passed. In normal operation, TEST is left open

(internally pulled high), disabling the pattern generator

and accepting data from the parallel input channels.

Test Loopbacks

Two additional test loopbacks are provided: parallel

system loopback and serial line loopback.

Parallel System Loopback

In parallel system loopback, four 622Mbps parallel

input channels are phase aligned by an associated 10-

bit elastic store and routed to the output LVDS buffers.

This loopback is controlled by setting PLBEN low.

Normal data transmission is resumed when PLBEN

goes high (internally pulled high).

Serial Line Loopback

Serial line loopback is used for testing the performance

of the optical transceiver and the transmission link. The

received 2.488Gbps data stream is routed to the trans-

mit CML output buffer. Line loopback is enabled when

LBEN is asserted low. When LBEN is left open (internally

pulled high), normal serial-data transmission resumes.

LVDS Parallel Interface

The MAX3831 parallel interface includes four OC-12

data inputs, a 155MHz reference clock input, four

622Mbps parallel-data outputs, and a 622MHz parallel-

inputs and outputs are LVDS compatible to minimize

power dissipation, speed transition time, and improve

noise immunity. The 155MHz input signal at RCLKI

requires a duty cycle between 40% and 60%.

The LVDS outputs go into a high-impedance state when

TRIEN is forced low. This simplifies system checks by

allowing vectors to be forced on the LVDS outputs.

CML Serial Interface

The MAX3831/MAX3832 provide a 2.488Gbps serial-

data stream to a driver and accept 2.488Gbps serial

data and a 2.488GHz clock signal from an external

clock and data recovery device (MAX3876). The high-

speed interface is CML compatible, resulting in lower

system power dissipation and excellent performance

(Figure 7).

__________Applications Information

Low-Voltage Differential

Signal Inputs/Outputs

The MAX3831/MAX3832 have LVDS inputs and outputs

for interfacing with high-speed digital circuitry. All LVDS

inputs and outputs are compatible with the IEEE-1596.3

LVDS specification. This technology uses 250mV to

400mV differential low-voltage amplitudes to achieve

fast transition times, minimize power dissipation, and

improve noise immunity.

For proper operation, the parallel clock and data LVDS

outputs (PCLKO+, PCLKO-, PDO_+, PDO_-) require

100

Ω differential DC termination between the inverting

and noninverting outputs. Do not terminate these out-

puts to ground. The parallel-data LVDS inputs (PDI_+,

PDI_-) are internally terminated with 100

Ω differential

input resistance and therefore do not require external

termination.

Interfacing with PECL/ECL

Input Levels

When interfacing with differential PECL input levels, it is

important to attenuate the signal while still maintaining

50

Ω termination (Figures 8 and 9). Observe the com-

mon-mode input voltage specifications. AC-coupling is

input common-mode level (Figure 8).

MAX3831

MAX3832

MAX3876

50

Ω

50

Ω

50

Ω

50

Ω

SDI+

SDI-

SDO+

SDO-

Figure 7. CML-to-CML Interface